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AMD Alchemy Au1550 Security Network Processor Data Book
Au1 Core and System Bus
30283D
The write buffer is a 16-word deep first-in-first-out (FIFO) queue. All processor stores arrive first at the merge latch, where
merging and gathering decisions are performed, and then travel through the queue. The write buffer arbitrates for the SBUS
to perform consolidated transfers to the main memory.
A write buffer FIFO entry contains the address (word address), the data and associated byte masks (BM), and two control
bits. The four BM bits indicate which bytes within the word contain valid data. The two control bits are the valid (V) bit which
indicates if the entry is valid, and the closed (C) bit. When a C bit is set, the write buffer initiates a request to the SBUS so
that it can transfer data to memory. The conditions in which the C bit is set are described below.
The write buffer is capable of variable-length burst writes to memory. The length can vary from one word to eight words, and
is determined by the C bits in the write buffer. During each beat of the burst, the appropriate bytes to write are selected from
the corresponding byte masks. As each word is written to memory, it is popped from FIFO entry 0, advancing each entry in
the FIFO by one.
As long as the write buffer has at least one empty entry, processor stores do not stall, thus improving processor perfor-
mance.
The write buffer is disabled by setting Config0[WD] to 1. In this instance, all non-cacheable and data cache store-misses
stall until the write completes. The remaining description of the write buffer operation assumes Config0[WD] is 0. Out of
reset, Config0[WD] is 0.
2.4.1
Merge Latch
All processor stores first arrive at the merge latch. Logic within the merge latch decides what action to take with the incom-
ing data, based on the incoming address:
1)
The incoming address is the same word address as the merge latch address. This case is for merging, which occurs
propagate to the write buffer FIFO.
2)
The incoming word address is sequentially adjacent to the merge latch word address (incoming address is merge latch
latch contents are propagated to the write buffer FIFO with the C bit cleared, and the incoming data is placed into the
merge latch.
3)
Neither 1 nor 2 is true. The merge latch contents are propagated to the FIFO with the C bit set, and the incoming data
is placed into the merge latch.
When the merge latch contents are propagated to the FIFO, the incoming address and data are placed in the merge latch
for future comparisons. Furthermore, if the incoming address is the last word address of the maximum burst size (the least
significant 5 bits are 0x1C), the C bit is set for the incoming address.
2.4.2
Write Buffer Merging
Write buffer merging combines stores destined for the same word address. Merging places the incoming data into the
appropriate data byte(s) within the merge latch.
Write buffer merging is particularly useful for sequential, incremental address write operations, such as string operations.
With write buffer merging, the writes are merged into 32-bit writes which reduces the number of accesses to the memory
and increases the effective throughput to main memory.
This example demonstrates merging. These five byte writes occur in sequence:
0x00001000 = 0xAB
0x00001001 = 0xCD
0x00001002 = 0xDE
0x00001003 = 0xEF
0x00001002 = 0xBE
After the first four writes, the data in the merge latch contains 0xABCDDEEF. However, after the fifth write, the merge latch
data now contains 0xABCDBEEF.
So long as the incoming word address is the same as the merge latch word address, the data can change without a proces-
sor stall or access to memory.