320
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
MII management frames transmitted through the MDIO pin are synchronized with the rising edge of the management data
clock (MDC). The Au1550 processor drives the MDC to 0 and tri-states the MDIO any time the MII management port is not
active.
The Au1550 processor communicates with the external PHY through the MII control register (mac_miictrl) and MII data
register (mac_miidata).
9.4.6
Programming the Ethernet MACs
Once configured, the Ethernet MACs receive and transmit packets with minimal software intervention. Each Ethernet MAC
is supported by two DMA engines which independently handle receiving and transmitting frames. Each DMA engine pro-
cesses a 4-entry ring from/into which packets are moved, as shown below.
There are two rings, one for transmit and one for receive. As the DMA engine completes an operation on an entry, it moves
on to the next entry in the ring. Status bits and interrupts indicate when the operation has completed.
A transmit DMA engine entry is composed of the macdma_txstat, macdma_txlen and macdma_txaddr register triplet. A
receive DMA engine entry is composed of the macdma_rxstat and macdma_rxaddr register pair. The Ethernet DMA
engines are dedicated engines, separate from the general purpose DMA controller.
The control of the MAC by software is described in the sections below. The discussion applies equally to both MACs; how-
ever, where coding examples are given, MAC0 is used.
9.4.6.1
Programming Considerations
When programming the MAC, take into consideration the following:
Before the MAC can be used, the entire MAC module must be enabled via the macen_mac0 register. An unused MAC is
disabled to reduce power consumption.
All register accesses must be 32-bits. Furthermore, 32-bit register accesses work for both endian modes. This is not true
for the buffer contents, which is independently controlled via mac_control[EM].
As with all peripherals integrated into the Au1550 processor, all register accesses are through the KSEG1 region. This
region is un-mapped, and more importantly, non-cached. All non-cached accesses proceed through the write buffer. As a
result, accesses to the MAC registers must flush the write buffer (before and/or) after a register write. Flushing the write
buffer also guarantees that previous writes have been posted to the peripheral. The write buffer is flushed with a SYNC
instruction (rather than a non-cached read since a read of a peripheral register can have unintended side-effects).
9.4.6.2
MAC Initialization
Initialization of the MAC is performed using these recommended steps:
1)
Pre-allocate four buffers for the receiver buffer DMA ring and four buffers for the transmitter buffer DMA ring.
2)
Place the MAC in reset. This is accomplished by writing the value 0x00000040 to the macen_mac0 register. This dis-
ables the entire MAC module and its DMA engines.
3)
Initialize the receive DMA ring. For each of the four DMA entries, write the address of a receive buffer along with EN=1
bit to the macdma_rxaddr register. The receive buffers must be cache line (32-byte) aligned.
0
1
2
3
DMA Engine Ent ries
Main M emory Buffers