AMD Alchemy Au1550 Security Network Processor Data Book
321
Ethernet MACs
30283D
4)
Initialize the transmit DMA ring. For each of the four DMA entries, write the value 0x00000000 to the macdma_txaddr
and macdma_txlen registers. The transmit buffers must be cache line (32-byte) aligned. The macdma_txaddr[EN] bit
must not be set until after step 10 is performed and a frame is constructed in memory and ready to be sent.
5)
Enable the MAC module by performing this sequence. The following steps must not be combined, but performed in
sequence:
– Write 0x00000041 to mac0_enable. This enable clocks to the MAC.
– Write 0x00000033 to mac0_enable. This takes the MAC out of reset, enables coherent transactions and passes
only valid frames to memory.
6)
Configure the MAC module.
– Write the mac_control register. The exact value varies depending on the application, but the value 0x00800000
works in most circumstances. mac_control[EM] indicates if the buffer contents are written by the processor in big
endian or little endian mode; if the processor is running in big endian, the value 0x40800000 is desired.
– Write the mac_addrhigh and mac_addrlow registers with the 48-bit Ethernet MAC address for this controller. For
example, if the MAC address is 01:23:45:67:89:AB, then mac_addrhigh is written with 0x0000AB89 and
mac_addrlow is written with 0x67452301.
– Write the mac_hashhigh and mac_hashlow registers with 0xFFFFFFFF. This value accepts all multicast frames
(if enabled by mac_control[PM,HO,HP] bits).
7)
Configure the MII. Consult the documentation for the PHY device for any special settings. Software must poll the
mac_miictrl[MB] bit before each MII access. The MAC and the PHY must agree on duplex; otherwise, collisions
between the MAC and the PHY occur on the MII interface and significantly degrade performance.
8)
Initialize a driver global variable named NextRxBuffer. This variable is initialized from the (macdma_rxaddr[CB] >> 2)
of any receive DMA entry. The CB field points to the entry that is processed next by the receive DMA engine. Its value
out of reset is not guaranteed to be zero.
9)
Initialize a driver global variable named NextTxBuffer and LastTxBuffer. Both variables are initialized from the
(macdma_txaddr[CB] >> 2) of any transmit DMA entry. The CB field points to the entry that is processed next by the
transmit DMA engine. Its value out of reset is not guaranteed to be zero.
10) Enable the transmit and receive DMA engines. Utilizing a read-modify-write operation, set the mac_control[TE,RE]
bits. Now enabled, Ethernet packet reception and transmission can occur.
The MAC is now operational.
9.4.6.3
MAC Interrupts
There are two possible options in configuring the interrupt controller, IC0, for MAC interrupts: rising edge or high level. The
reason for the two options is a result of the interrupt logic. The MAC interrupt signal is a logical OR’ing of all the DN bits in
the macdma_rxaddr and macdma_txaddr DMA registers. When a DMA entry is consumed, the DN bit transitions from a
0 to 1, thus a rising edge interrupt is possible. Similarly, as long as a DN bit is set, high level interrupts are also possible.
The DN bit is cleared only by software when handling a completed DMA entry.
The interrupt controller, IC0, for MAC interrupts (interrupt 27 for MAC0 and interrupt 28 for MAC1) is configured as rising-
edge or high-level. If the MAC interrupt is configured for rising-edge, then it must be acknowledged by writing 1 to the corre-
sponding bit in ic0_risingclr in IC0. The receive and transmit algorithms described below work with either interrupt type.
However, the use of rising edge interrupts requires a mature driver (to avoid the race condition of taking the interrupt,
acknowledging the interrupt and receiving additional interrupts while handling the interrupt). Thus, many drivers choose to
utilize high-level interrupts, which is more forgiving during driver development, and generally more robust as interrupts are
not easily lost.
When a MAC interrupt does occur, software must examine the DMA entries; there is no interrupt status register to check.
Since the receiver cannot throttle traffic, most applications first handle the receive buffers and then the transmit buffers. In
other words, the interrupt service routine for the MAC calls the MAC receive algorithm and then the MAC transmit algorithm.
The algorithms are designed to process zero or more completed buffers.
If the application is polled rather than interrupt-driven, it too calls the MAC receive and transmit algorithms described below,
since they are designed to process zero or more completed buffers.