AMD Alchemy Au1550 Security Network Processor Data Book
319
Ethernet MACs
30283D
MII Transmit Interface
The MII transmit clock is generated by the external PHY and is sent to the Au1550 processor on the TX_CLK input pin. The
clock can run at 25 MHz or 2.5 MHz, depending on the speed of the network to which the external PHY is attached. The
data is a 4-bit data path, TXD[3:0], from the Au1550 processor to the external PHY and is synchronous with the rising edge
of TX_CLK. The transmit process starts when the Au1550 processor asserts TX_EN, which indicates to the external PHY
that the data on TXD[3:0] is valid.
The Au1550 processor does not implement the TX_ER function; the TX_ER pin on the external PHY device is connected to
VSS.
MII Receive Interface
The MII receive clock is also generated by the external PHY and is sent to the Au1550 processor on the RX_CLK input pin.
The clock is the same frequency as the TX_CLK but is out of phase and can run at 25 MHz or 2.5 MHz, depending on the
speed of the network to which the external PHY is attached.
The receive process starts when RX_DV is asserted. RX_DV must remain asserted until the end of the receive frame. The
Au1550 processor does not implement the RX_ER function.
MII Network Status Interface
The MII also provides the CRS (Carrier Sense) and COL (Collision Sense) signals that are required for IEEE 802.3 opera-
tion. Carrier Sense is used to detect non-idle activity on the network for the purpose of inter-frame spacing timing in half-
duplex mode. Collision Sense is used to indicate that simultaneous transmission has occurred in a half-duplex network.
MII Management Interface
The MII provides a two-wire management interface so that the Au1550 processor can control external PHY devices and
receive status from them.
The MAC can be programmed to send a management frame to the PHY to determine auto-negotiation results and the cur-
rent link status.
MII Management Frames
The format of an MII management frame is defined in Clause 22 of IEEE Std 802.3; see
Figure 9-4. The start of an MII
management frame is a preamble of 32 ones that guarantees that the external PHYs are synchronized on the same inter-
face.
Figure 9-4. MII Management Frame Format
The preamble (if present) is followed by a start field (ST) and an operation field (OP). The operation field (OP) indicates
whether the Au1550 processor is initiating a read or write operation. This field is followed by the external PHY address
(PHYAD) and the register address (REGAD). The PHY address of 0x1F is reserved and not to be used.
The register address field is followed by a bus turnaround field (TA). During a read operation, the bus turnaround field is
used to determine if the external PHY is responding correctly to the read request.
During the second cycle of a read operation, if the external PHY is synchronized to the Au1550 processor, the external PHY
drives a 0. During a write access the Au1550 processor drives a 1 for the first bit time of the turnaround field and a 0 for the
second bit time.
After the turnaround field comes the data field. For a write access the Au1550 processor fills this field with data to be written
to the PHY device. For a read access the external PHY device fills this field with data from the selected register.
The last field of the MII management frame is an IDLE field that is necessary to give ample time for drivers to turn off before
the next access.
Preamble
1111… 1111
ST
01
PHY
Address
Register
Address
32
Bits
2
Bits
5
Bits
5
Bits
OP
10 Read
2
Bits
01 Write
TA
Z0 Read
2
Bits
10 Write
Data
16
Bits
Idle
Z
1
Bit