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AMD Alchemy Au1550 Security Network Processor Data Book
Static Bus Controller
30283D
3.2.3
PCMCIA/Compact Flash Device Type
Because of the similarity of Compact Flash and PCMCIA, references to PCMCIA should be taken as applicable to Compact
Flash except where noted. The PCMCIA peripheral is designed to the PCMCIA2.1 specification—but only for the bus trans-
actions as described in this section.
The Au1550 processor provides a PCMCIA host adapter when the device type is programmed for PCMCIA. The static bus
controller interface provides the required bus signals necessary to control a PCMCIA interface. Auxiliary signals, such as
card detect and voltage sense, can be implemented with GPIOs if desired. Synchronous mode (mem_stcfg[S] = 1) is not
available for PCMCIA.
The PCMCIA host interface adapter supports memory, attribute, and I/O transactions. External logic can be added to sup-
port DMA transfers.
The Au1550 processor supports only 8- and 16-bit load and store instructions (byte and halfword instructions) to PCMCIA
devices. 32-bit transfers are not supported. Note the following about PCMCIA transfers:
For writes, the static bus controller uses the internal SBUS byte masks to extract the data from sysbus_data.
For reads, the static bus controller replicates the read-data into sysbus_data; that is, for an 8-bit access, the read-data is
replicated into all four bytes of sysbus_data, and for a 16-bit access, the read-data is replicated into both halfwords of
sysbus_data. This behavior enables Au1 core loads and stores to operate correctly in either endian mode for PCMCIA.
The PCMCIA interface occupies a 36-bit address space with sysbus_addr[35:32] = 0xF. The TLB is required to generate
addresses that activate a PCMCIA chip select. I/O, memory and attribute spaces are differentiated by sysbus_addr[31:30].
The PCMCIA interface provides control signals defined for PCMCIA slots. If two cards are required, external logic must be
added to allow for both cards to share the bus. When a chip select is programmed as a PCMCIA device, the associated
RCSn# is not used.
Table 3-14 shows the signals supporting the PCMCIA interface.
Table 3-13. PCMCIA Memory Mapping
Physical Address (Note 1)
Note 1. Each of the PCMCIA physical address spaces has a maximum size of 64 Mbytes. An access beyond the 64 Mbyte
space aliases back into the defined region.
PCMCIA Mapping
0xF 0xxx xxxx
I/O
0xF 4xxx xxxx
Attribute
0xF 8xxx xxxx
Memory
Table 3-14. PCMCIA Interface Signals
Pin Name
Input/Output
Description
RAD[28:0]
O
Address bus
RD[15:0]
IO
Data bus
PREG#
O
When this signal is asserted card access is limited to attribute memory when a
memory access occurs and to I/O ports when an I/O access occurs.
PCE[2:1]#
O
Card Enables
POE#
O
Memory Output enable
PWE#
O
Memory Write Enable
PIOR#
O
I/O Read Cycle Indication
PIOW#
O
I/O Write Cycle Indication
PWAIT#
I
This signal is asserted by the card to delay completion of a pending cycle. This
signal must be tied high through a resistor when the PCMCIA interface is not
used.