178
AMD Alchemy Au1550 Security Network Processor Data Book
Security Engine
30283D
7.3.4
Command Queue Registers
The real-time operation of the Packet Engine is controlled by packet descriptors which are written into a Command Queue
which is a register set that drives the Packet Engine (PE). The Command Queue consists of five 32-bit words.
When the host writes a command to the Command Queue, the command is triggered when the last word (Control_2/
Length) of the structure is written. This ensures that the other fields are correct before the command is executed.
7.3.4.1
Packet Descriptors
When the Descriptor Ring mode is enabled, descriptors are automatically fetched from a descriptor ring in memory and
placed into the internal command queue for processing. The format of a packet descriptor is the same as shown above for
the Command Queue.
Table 7-9 on page 178 (above) shows the format of a packet descriptor when it resides in the command queue; however,
endian swapping may affect the byte arrangement as seen by the host processor:
When the host writes descriptors into the command queue, sec_dmaendian[SBLn] determines if there are byte-lane
When descriptors are fetched from an external location using the descriptor fetch engine, sec_dmaendian[MBLn] may
Packet descriptors are typically word-aligned, but it is not required.
7.3.4.2
Command Queue Control/Status Register
The Command Queue Control/Status (sec_qctrlstat) provides the command information to the Packet Engine. Together
with the data pointed to in the SA structure, this provides the Packet Engine its instructions for processing a packet.
Once the requested operation has completed, successfully or unsuccessfully, this register provides result status in bits
[23:16]. The status is a read-only field in the Result Descriptor only. (It is a “don’t care” in the packet descriptor.) The status
field encodes the result status for the operation requested in the corresponding Packet Descriptor. Many of the status code
values are valid only for inbound protocol operations. A successful “normal” completion status byte is 0x00. A packet failure
condition is indicated by a non-0 first nibble (bits 16:19). A 0000 first nibble and a non-0 upper nibble indicates a “Notifica-
tion” code which is not necessarily a failed packet.
Table 7-9. Command Queue and Descriptor Format
Byte Offset
31
24
23
16
15
8
7
0
00
Pad Control/Status
Status
Next Header/Pad
Control
04
Source Address
08
Destination Address
0C
SA Handle
10
Reserved
Control_2
Packet Length (bytes)
sec_qctrlstat
Offset = 0x0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PCS
EC
EE SN PV
A
NH
HF NK LHD ED HD
Def. 00000000000000000000000000000010