AMD Alchemy Au1550 Security Network Processor Data Book
221
Serial Peripheral Interface (SPI) Controller
30283D
8.2.1.6
SPI Tx/Rx Data Register
The SPI Tx/Rx data register (psc_spitxrx) is the interface to the transmit and receive FIFOs. Each FIFO is 16 entries deep.
A write to this register causes data to be pushed onto the Tx FIFO; if the Tx FIFO is already full, the data is lost and a trans-
mit-overflow event is triggered (psc_spievnt[TO] = 1). A read from this register causes data to be popped from the Rx
FIFO; if the Rx FIFO is already empty, the data read is undefined and a receive-underflow event is triggered
(psc_spievnt[RU] = 1).
If transfers are under program control (psc_spicfg[DD] = 1), software can monitor the transmit-request (TR) and receive-
request (RR) flags to maintain proper FIFO levels either by polling psc_spistat[TR, RR] or by waiting for interrupts in
psc_spievnt[TR, RR]. The DDMA controller (psc_spicfg[DD] = 0) automatically manages overflow/underflow conditions.
The data size of read/write transfers is always 32-bits to the register; however, depending on the data length value
(psc_spicfg[LEN]) all unused bits must be 0s.
When DMA transfers are enabled, the psc_spitxrx address locations must be programmed into the Tx descriptor destina-
tion pointer and the Rx descriptor source pointer.
13
RR
Receive Request. Applies to programmed I/O only (psc_spicfg[DD]=1).
Indicates the Rx FIFO has a number of data elements equal to the FIFO
threshold programmed in psc_spicfg[RT] available for reading.
R/W
0
12
RO
Receive Overflow. Indicates the Rx FIFO has experienced an overflow.
R/W
0
11
RU
Receive Underflow. Indicates the Rx FIFO has experienced an underflow.
R/W
0
10
TR
Transmit Request. Applies to programmed I/O only (psc_spicfg[DD]=1).
Indicates the Tx FIFO is requesting a number of data elements equal to
the FIFO threshold programmed in psc_spicfg[TT].
R/W
0
9
TO
Transmit Overflow. Indicates the Tx FIFO has experienced an overflow.
R/W
0
8
TU
Transmit Underflow. Indicates the Tx FIFO has experienced an underflow.
R/W
0
7:6
-
Reserved.
-
0
5
SD
Slave Done. Indicates a SPI Slave transfer has completed.
R/W
0
4
MD
Master Done. Indicates a SPI Master transfer has completed.
R/W
0
3:0
-
Reserved.
-
0
psc_spitxrx
Offset = 0x001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
LC ST
DATA
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:30
—
Reserved.
-
29
LC
Last Character. Applies to master mode only. When not using DMA, write a
1 to LC with the last character of the current transfer.
W0
28
ST
Slave Select Toggle. Available only on PSC0 and PSC1. Writing a 1 to ST
along with the character causes the PSC to toggle the slave select signal
after the transfer of the character.
W0
27:24
—
Reserved.
-
23:0
DATA
SPI Character Data. Bit 0 is the LSb.
R/W
0
Bits
Name
Description
R/W
Default