116
AMD Alchemy Au1550 Security Network Processor Data Book
PCI 2.2 Bus Controller
30283D
4.1.1.8
PCI Posted Read Address Register
The pci_praddr register is written with the 32-bit PCI read address. Writing this register enables the posted read state
machine and (assuming the PCI is not currently busy) a master read is performed on PCI. While the master read is pend-
ing, the posted read pending status bit is set (pci_prstat[PND] = 1), and all SBUS read/writes regarding posted reads are
ignored until the transaction has completed. This register must be written only after the posted read configuration register
(pci_prcfg) has been configured.
4.1.1.9
PCI Posted Read Status Register
The pci_prstat register contains the posted read pending flag (PND), the posted read done interrupt (DI), and the posted
read aborted interrupt (AI). These flags indicate the status of a posted read. Upon writing the posted read address register,
the pending flag is set. The pending flag remains set until the posted read has completed. If the posted read is successful,
the done interrupt is set. If the posted read is aborted, the abort interrupt is set. An abort/done interrupt is cleared by writing
a 1 to their bit locations; writing a 0 has no effect. The abort/done interrupts are maskable using the posted read interrupt
mask bits pci_prcfg[AM, DM].
4.1.1.10
PCI Posted Read Line Buffer
Upon the successful completion of a posted read (after the done flag has been set), the line buffer contains up to 8 words of
data from the previous posted read. This data is read by performing a burst read to the 36-bit address stored in the posted
read control registers ((pci_prcfg[ADDR_HIGH], pci_praddr[ADDR]}). Once the data has been read from the line buffer,
the done flag (PR_DONE) is cleared and the data is no longer valid.
4.1.2
PCI Configuration Registers
The following registers are defined in PCI Local Bus Specification, revision 2.2. These registers are visible from the PCI bus
as configuration space when the Au1550 is operating in satellite mode. When the Au1550 processor is operating in host
mode these registers are available in the local configuration register block. For detailed description of these registers and
their fields please refer to PCI Local Bus Specification, revision 2.2.
pci_praddr
Offset = 0x0028
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
ADDR
Def. 10001100101001100000000000101000
Bits
Name
Description
R/W
Default
31:0
ADDR
This is the 32-bit PCI address for a posted read.
R/W
0x8CA60028
pci_prstat
Offset = 0x002C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
AI
DI
PND
Def. xxxxxxxxxxxxxxxxxxxxxx
0
xxxxxxx
0
Bits
Name
Description
R/W
Default
31:10
—
Reserved.
-
9
AI
Posted read abort interrupt. Indicates a posted read has been aborted.
Write a 1 to this location to clear the interrupt.
R/W
0
8
DI
Posted read done interrupt. Indicates a posted read has successfully com-
pleted. Write a 1 to this location to clear the interrupt.
R/W
0
7:1
—
Reserved.
-
0
PND
Posted read pending. Indicates a posted read is in progress on the PCI
bus.
R0