AMD Alchemy Au1550 Security Network Processor Data Book
33
Au1 Core and System Bus
30283D
2.8
Coprocessor 0 Implementation
Coprocessor 0 (CP0) is responsible for virtual memory, cache, and system control.
The MIPS32 ISA provides for differentiation of the CP0 implementation. The Au1 core has a unique CP0 that is compliant
with MIPS32 specification. This section describes the CP0 registers as implemented in the Au1 core.
Table 2-7 lists the CP0 registers as defined by the MIPS32 ISA.
Table 2-7. Coprocessor 0 Registers
Register
Number
Sel
Register Name
Description
Compliance (Note 1)
Note 1.
A compliance of Required denotes a register required by the MIPS32 architecture. Optional denotes an optional register in the
MIPS32 architecture which is implemented in the Au1 core. Au1 denotes a register unique to the Au1 core. Reserved denotes a
register that is not implemented.
0
Index
Pointer into TLB array
Required
1
0
Random
Pseudo-random TLB pointer
Required
2
0
EntryLo0
Low half of TLB entry for even pages
Required
3
0
EntryLo1
Low half of TLB entry of odd pages
Required
4
0
Context
Pointer to a page table entry
Required
5
0
PageMask
Variable page size select
Required
6
0
Wired
Number of locked TLB entries
Required
7
0
Reserved
8
0
BadVAddr
Bad virtual address
Required
9
0
Count
CPU cycle count
Required
10
0
EntryHi
High half of TLB entries
Required
11
0
Compare
CPU cycle count interrupt comparator
Required
12
0
Status
Required
13
0
Cause
Reason for last exception
Required
14
0
EPC
Program Counter of last exception
Required
15
0
PRId
Processor ID and Revision
Required
16
0
Config0
Configuration Register 0
Required
1
Config1
Configuration Register 1
Required
17
0
LLAddr
Load Link Address
Optional
18
0
WatchLo
Data memory break point low bits
Optional
1
IWatchLo
Instruction fetch breakpoint low bits
Optional
19
0
WatchHi
Data memory break point high bits
Optional
1
IWatchHi
Instruction fetch breakpoint high bits
Optional
20-21
0
Reserved
22
0
Scratch
Scratch register
Au1
23
0
Debug
EJTAG control register
Optional
24
0
DEPC
PC of EJTAG debug exception
Optional
25
0
Reserved
26-27
0
Reserved
28
0
DTag
Data cache tag value
Au1
1
DData
Data cache data value
Au1
29
0
ITag
Instruction cache tag value
Au1
1
IData
Instruction cache data value
Au1
30
0
ErrorEPC
Program counter at last error
Required
31
0
DESave
EJTAG debug exception save register
Optional