AMD Alchemy Au1550 Security Network Processor Data Book
119
PCI 2.2 Bus Controller
30283D
4.2
Au1550 Processor Implementation Specifics
The following sections describe Au1550 implementation specific issues.
4.2.1
PCI Clock Generation
The Au1550 processor provides the capability to internally generate a clock on the PCI clock output pin PCI_CLKO. For
systems where internal generation of the PCI clock is insufficient, the Au1550 processor also provides the option to use an
externally generated PCI clock. The PCI bus must run at the same speed or slower than the SBUS.
4.2.2
Clock Connections
For internal PCI clock generation, the PCI_CLKO pin is used to generate the PCI clock. The generated clock must be fed
back into the PCI_CLK pin to drive the PCI interface logic. If an externally generated clock is used, the clock needs to be
driven into the PCI_CLK pin, and the PCI_CLKO pin is left unconnected.
4.2.3
Limitations on Internal PCI Clock Generation
The internal frequency generation circuitry of the Au1550 processor is flexible, but there are limitations on the frequencies
that can be generated. Either the CPU PLL or the AUX PLL may be used as the root source of the PCI clock generator. The
AUX PLL has the advantage that it is independent of CPU frequency. However, the system designer must take into account
that the AUX PLL is also used to generate the USB clocks, which are required to be 48 MHz.
All of the frequencies in the system are generated from the 12 MHz oscillator. The AUX PLL multiplies the 12 MHz clock by
the value in sys_auxpll, which is then divided by the frequency generators to reach the target frequency. The frequency
generators can be programmed to divide only by even values, which places further constraints on the available frequencies.
If the AUX PLL is to be used to generate both the USB clock and the PCI clock, it can be programmed to 384 MHz by pro-
gramming the sys_auxpll register to 32. This allows generation of the 48 MHz USB clock by setting the frequency genera-
tor to divide by eight. Setting a frequency generator to divide by six can generate a 64 MHz PCI clock, or dividing by twelve
can generate a 32 MHz clock. If the AUX PLL is not used for USB clock generation, it can be programmed to 396 MHz and
yield 66 MHz and 33 MHz with the same dividers. Alternately, if the CPU is being run at 396 MHz, the CPU PLL can be
used as the root clock for a frequency generator with the same effect.
4.2.4
Programming Example
The AUX PLL frequency is programmed by writing to sys_auxpll. The value written is multiplied by twelve to yield the
resulting PLL frequency. The following configuration example uses the AUX PLL and results in a 64 MHz PCI clock on the
PCI_CLKO pin:
1)
Write 0x0020 to sys_auxpll for an AUX PLL frequency of 384 MHz.
2)
Choose a frequency generator for the PCI clock by programming the sys_clksrc register:
– Write 0b100 to the MPC field. (For this example frequency generator 2 is used.)
– Clear the CPC bit so that the PCI clock is not further divided.
3)
Program the sys_freqctrl0 register:
– Program the FRDIV2 field to 0x0002 so that the frequency is divided by six.
– Set the FE2 bit to enable output from frequency generator 2.
– Set the FS2 bit to select the AUX PLL as the clock source.