AMD Alchemy Au1550 Security Network Processor Data Book
115
PCI 2.2 Bus Controller
30283D
4.1.1.5
PCI Error Address Register
This register captures the address of target writes, master reads and master writes that result in errors. The upper 4 bits of
This address is intended to be used in conjunction with the PCI header error bits described in the PCI 2.2 specification. The
error address captured is valid when pci_config[EF] or pci_config[EP] is set. The address for target write errors may not
be the specific identical error address due to synchronization issues. If multiple errors occur, this register contains the
address of the first error.
4.1.1.6
PCI Special/Int Ack Register
This register allows the programmer to initiate special and interrupt acknowledge cycles on the PCI bus. A read to this reg-
ister invokes an interrupt acknowledge cycle, and a write executes a special cycle. The register value read is undefined and
the actual value written is ignored.
4.1.1.7
PCI Posted Read Configuration Register
The pci_prcfg register contains the posted read PCI burst size (BS), bits [35:32] of the 36-bit System Bus (SBUS) address
(ADDR_HIGH) and the posted read interrupt masks. Burst size dictates how many words are read on the PCI bus during
the master read transaction. This register must be configured before performing a posted read.
pci_erraddr
Offset = 0x001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
ERRADDR[31:0]
Def. 00000000000000000000000000000000
pci_specintack
Offset = 0x0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SPECINTACK[31:0]
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
pci_prcfg
Offset = 0x0024
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
BLM
AM DM
BS
ADDR_HIGH
Def. xxxxxxxxxxxxxxxx
0000
x
00
x
0100100
Bits
Name
Description
R/W
Default
31:16
—
Reserved.
-
15:12
BLM[3:0]
Byte lane mask. When BLM[n] is set, the corresponding byte lane is
masked out.
BLM[3] masks PCI_AD[31:24].
BLM[2] masks PCI_AD[23:16].
BLM[1] masks PCI_AD[15:8].
BLM[0] masks PCI_AD[7:0].
R/W
0
11:10
—
Reserved
--
9
AM
Posted read abort interrupt mask.
0
Enable the posted read abort interrupt.
1
Disable the posted read abort interrupt.
R/W
0
8
DM
Posted read done interrupt mask.
0
Enable the posted read done interrupt.
1
Disable the posted read done interrupt.
R/W
0
7
—
Reserved.
-
6:4
BS
Posted read burst size. Contains the burst size for a posted read. Valid
burst size is between 1 and 8 words.
The actual burst size is (BS + 1).
R/W
0x2
3:0
ADDR_HIGH
Address high. Contains bits [35:32] of the 36-bit SBUS address.
R/W
0x4