142
AMD Alchemy Au1550 Security Network Processor Data Book
Descriptor-Based DMA (DDMA) Controller
30283D
5.3.1.7
Destination 1 (1-Dimensional Stride)
This entry in the descriptor contains the block and stride values for the destination transfer. For stride transfers, the format
of the entry depends on the type of stride.
5.3.1.8
Destination Block/Stride (2 Dimensional)
This entry in the descriptor contains the block and stride values for the destination transfer. For stride transfers, the format
of the entry depends on the type of stride.
dscr_dest1 (1-Dimensional Stride)
Offset = 0x14
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DTS
DAM
DB
DS
Bits
Name
Description
31:30
DTS
Destination Transfer Size. Selects the number of datums transferred per SBUS grant for a destination
transfer.
00
1 datum
01
2 datums
10
4 datums
11
8 datums
29:28
DAM
Destination Address Movement. For each destination access, the address:
00
Increments
01
Decrements. The source pointer must be the fourth byte of a word-aligned address. For example, if
the first source word is 0xA1000000, the source pointer should be 0xA1000003. Byte count can be
any multiple of the source width. Source transfer size must be 0 (1 datum).
10
Remains static (FIFO). Not valid for stride transfers.
11
Remains static but burstable (burstable FIFO). Not valid for stride transfers. For burstable FIFOs, the
static bus controller continues to increment the lower address bits during the burst transfer. The
external FIFO must ignore the lower address bits that change during the burst. Each access must be
aligned to the total transfer size.
27:14
DB
Destination Block Size. Specifies the number of bytes transferred to the destination before the stride
value is added/subtracted to/from the destination address.
13:0
DS
Destination Stride. Specifies the stride of the transfer and is added/subtracted to/from the destination
address after the block size (DB) has been transferred. If DAM is programmed to increment, the stride is
added to the destination address. If the DAM is programmed to decrement, the stride is subtracted from
the destination address.
Clear DS to disable destination stride.
dscr_dest1 (2-Dimensional Stride)
Offset = 0x14
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DTS
DAM
DB
DS
DSC
Bits
Name
Description
31:30
DTS
Destination Transfer Size. Selects the number of datums transferred per SBUS grant for a destination
transfer.
00
1 datum
01
2 datums
10
4 datums
11
8 datums