232
AMD Alchemy Au1550 Security Network Processor Data Book
Inter-IC Sound Controller (I2S)
30283D
8.3.1.4
I2S Status Register
The I2S Status register (psc_i2sstat) contains all the status signals for the I2S protocol. It is read-only. A status condition is
true when the status bit is set. Before the I2S controller is enabled in psc_i2scfg[DE], only the device-ready and PSC-
ready status bits (psc_i2sstat[DR, SR]) are valid; all other status bits read as 0 until ready.
8.3.1.5
I2S Event Register
The I2S Event register (psc_i2sevnt) contains the event flags for the I2S protocol, as well as the FIFO event flags. Status
changes are flagged in the event register. Each event triggers an interrupt unless masked in the I2S mask register
(psc_i2smsk).
Once an event flag is set, it remains set until software clears it. A flag is cleared by writing a 1 to the appropriate bit; writing
a 0 has no effect.
psc_i2sstat
Offset = 0x0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RF RE RR TF TE TR
RB TB
DI DR SR
Def. 00000000000000000001001000000000
Bits
Name
Description
R/W
Default
31:14
-
Reserved.
-
0
13
RF
Receive FIFO Full.
R
0
12
RE
Receive FIFO Empty.
R
1
11
RR
Receive Request.
R
0
10
TF
Transmit FIFO Full.
R
0
9
TE
Transmit FIFO Empty.
R
1
8
TR
Transmit Request.
R
0
7:6
-
Reserved.
-
0
5
RB
Receive Busy. Indicates the controller is currently receiving data.
R
0
4
TB
Transmit Busy. Indicates the controller is currently transmitting data.
R
0
3
-
Reserved.
-
0
2
DI
Device Interrupt. Indicates at least one unmasked event has been flagged
in psc_i2sevnt.
R0
1
DR
Device Ready. Indicates the I2S controller is ready for protocol operation
after setting the device-enable bit psc_i2scfg[DE].
R0
0
SR
PSC Ready. Indicates the PSC is ready for protocol configuration after
enabling the PSC in psc_ctrl[ENA].
R0
psc_i2sevnt
Offset = 0x0018
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RR RO RU TR TO TU
RD TD
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:14
-
Reserved.
-
0
13
RR
Receive Request. Applies to programmed I/O only (psc_i2scfg[DD]=1).
Indicates the Rx FIFO has a number of data elements equal to the FIFO
threshold programmed in psc_i2scfg[RT] available for reading.
R/W
0
12
RO
Receive Overflow. Indicates the Rx FIFO has experienced an overflow.
R/W
0
11
RU
Receive Underflow. Indicates the Rx FIFO has experienced an underflow.
R/W
0
10
TR
Transmit Request. Applies to programmed I/O only (psc_i2scfg[DD]=1).
Indicates the Tx FIFO is requesting a number of data elements equal to
the FIFO threshold programmed in psc_i2scfg[TT].
R/W
0
9
TO
Transmit Overflow. Indicates the Tx FIFO has experienced an overflow.
R/W
0
8
TU
Transmit Underflow. Indicates the Tx FIFO has experienced an underflow.
R/W
0