238
AMD Alchemy Au1550 Security Network Processor Data Book
Inter-IC Sound Controller (I2S)
30283D
8.3.2.3
I2S Configuration
1)
Enable or disable DMA transfers (psc_i2scfg[DD]). The I2S controller can operate in either mode.
2)
3)
Enable the PSC for I2S operation. Poll the psc_i2sstat[SR] bit to see if the PSC is ready.
4)
Configure I2SWORD, I2SMCLK, and I2SCLK for the required sample rate. I2SMCLK is configured as an input
(psc_sel[CLK] = 01). For PSC3 only, I2SMCLK can also be internally generated (psc_sel[CLK] = 00).
If the controller is configured to generate I2SWORD, I2SCLK, and I2SMCLK (for PSC3 only), the signals begin to transmit
regardless of the controller status once the device is enabled. In this condition, the controller is idle: no data is being trans-
mitted, and I2SDO is held low or receiving.
8.3.2.4
I2S Transmit
1)
Enable DMA transfer or fill Tx FIFOs with data. Software must load channel data in the required order. Left channel
data is loaded first.
2)
Set the Tx Start bit (psc_i2spcr[TS] = 1) to start the data transfer. The Tx Busy status (psc_i2sstat[TB]) can be
checked to determine if the controller has engaged.
3)
I2S controller checks for two valid Tx data elements before sending the first one to ensure it maintains synchronization
with I2SWORD. A transmit underflow (psc_i2sevnt[TU] = 1) results if this condition is not met. Both left and right chan-
nels transmit at this time. If an underflow condition occurs, Tx FIFOs must be loaded before clearing the interrupt to
avoid causing another transmit underflow interrupt from empty FIFOs. Software can monitor for an underflow condition
to make sure all data has been sent.
The I2S transmit controller sends either buffered Tx data or a preset Tx data element (depending on the configuration) for
both channels of the current frame. This prevents synchronization loss on I2SWORD strobe.
To disable the transmitter, set the psc_i2spcr[TP] bit. Data stops transmitting at the end of the current frame. While the
transmitter is disabled, it continues to write zeros on each channel.
While the transmitter is disabled, the Tx FIFO can be cleared by setting the transmit-clear bit (psc_i2spcr[TC] = 1). Any
data in the FIFO is transmitted upon enabling the transmitter.
8.3.2.5
I2S Receive
See
Figure 8-10 on page 237 for reference. The Rx controller operates independently of the Tx controller. Either can be
enabled or disabled without affecting the other.
1)
Enable DMA (if used) for L/R channel receive. For DMA transfers into memory, the descriptors must have a byte count
that is evenly divisible by the size of a channel pair (data length x 2).
2)
Set the Rx Start bit (psc_i2spcr[RS] = 1) to start receiving. Poll status busy (psc_i2sstat[RB]) to see when the con-
troller has engaged.
3)
If at least two entries are not available in the Rx FIFO, an overflow occurs (psc_i2sevnt[RO] = 1). In this case, an over-
flow interrupt is triggered unless it is masked. An overflow results in the loss of data for both channels. Two entries are
always required to maintain data synchronization with I2SWORD. If at least two entries are available, both channels
are received and pushed into the Rx FIFO. The process continues for each frame.
4)
For an Rx overflow, reads from the FIFO must occur to make available at least two empty entries. Software must then
clear the overflow interrupt to avoid multiple interrupts for the same condition.
5)
Set the interrupt-enable bit in the last Rx descriptor (if DMA used) when the last packet is received. The receiver can
be disabled on that interrupt.
6)
Similar to the transmitter, the receiver stops at the end of the current frame when disabled (psc_i2spcr[RP] = 1). The
Rx busy bit indicates if the controller has been disabled. The receiver ignores incoming data while disabled.
7)
While the receiver is disabled, the Rx FIFO can be cleared by setting the receive-clear bit (psc_i2spcr[RC] = 1).