AMD Alchemy Au1550 Security Network Processor Data Book
171
Security Engine
30283D
7.3.3
Packet Engine Global Registers
Table 7-8 lists the registers which apply to the entire PE subsystem.
7.3.3.1
DMA Configuration Register
The packet engine DMA configuration register (sec_glbdmacfg) selects static settings which control the packet processing
path. These settings are typically set at initialization and not changed again.
Table 7-8. Packet Engine Global Registers
Offset (Note 1)
Register Name
Description
0x0040
sec_glbdmacfg
DMA configuration
0x0044
sec_glbdmastat
DMA status
0x0048
sec_glbpdrbase
Packet descriptor base address
0x004C
sec_glbrdrbase
Result descriptor base address
0x0050
sec_glbrsize
Ring size
0x0054
sec_glbrpoll
Ring poll
0x0058
sec_glbqstat
Command queue status
0x005C
sec_glbextrstat
External ring status
0x0060
sec_glbthresh
I/O buffer thresholds
0x0064 – 0x007F
—
Reserved
sec_glbdmacfg
Offset = 0x0040
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SUP
EP ESAEPD
PFD SAP PE
RP RPE
Def. 00000000000111110101000001010000
Bits
Name
Description
R/W
Default
31:21
—
Reserved.
R/W
0
20
SUP
Suppress PDR Ownership Update. Determines whether the security
engine updates the ownership bits in the packet descriptor on the PDR.
This setting is ignored if the PDR and RDR overlap.
0
The security engine clears the ownership bits of the packet descriptor
when it finishes an operation. This prevents the security engine from
re-processing an ‘old’ descriptor when it wraps around the PDR.
1
The security engine does not clear the ownership bits in the packet
descriptor when it completes an operation. In this case, the host
application is responsible for clearing the ownership bits. The host
must clear these ownership bits before the security engine is allowed
to wrap entirely around the PDR to re-encounter old descriptors.
(This does not occur as long as at least one descriptor not owned by
the security engine separates the newest valid descriptor and the old-
est.) Choosing this setting has the advantage of eliminating a sepa-
rate DMA write to the PDR. Of course, the Result Descriptor is
always written by the security engine.
R/W
1
19
—
Reserved.
R/W
1