322
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
9.4.6.4
MAC Frame Receive
The algorithm for processing buffers which the receive DMA engine has filled is simple and robust. Its robustness is due to
the fact that it can handle zero or more completed buffers, independent of whether the driver is interrupt driven or polled.
The algorithm pseudo-code is:
while (macdma_rxaddr[NextRxBuffer].DN == 1)
{
Examine macdma_rxstat[NextRxBuffer].FA for errors
If no errors, process buffer contents
Zero macdma_rxstat[NextRxBuffer]
Write macdma_rxaddr[NextRxBuffer] with memory buffer address and DN=0,EN=1 // clear IRQ
Advance NextRxBuffer: if (++NextRxBuffer == 4) NextRxBuffer = 0
}
This algorithm assumes that the same memory buffer is used for the same DMA entry. The receive algorithm is changed to
accommodate managing multiple memory buffers for the DMA entries. It is necessary to write the address of the memory
buffer every time to macdma_rxaddr since the DMA engine modifies the value in the register.
In the event that the DMA engine discovers that the next buffer entry is not yet available (macdma_rxaddr[EN]=0), the
engine stalls until the EN bit is set by software. In other words, frames are dropped and the CB field does not advance until
the buffer entry becomes available again. There is no mechanism for reporting that frames have been dropped.
9.4.6.5
MAC Frame Transmit
The algorithm for transmitting frames is also straightforward. This code to transmit a frame is independent of whether the
driver is interrupt driven or polled. The algorithm pseudo-code is:
// Handle previously transmitted frames
while (1)
{
if (macdma_txaddr[LastTxBuffer].DN == 1)
{
Examine macdma_txstat[LastTxBuffer] for errors
Write macdma_txaddr[LastTxBuffer].DN=0 // clear IRQ
Advance LastTxBuffer: if (++LastTxBuffer == 4) LastTxBuffer = 0
If (LastTxBuffer == NextTxBuffer) BREAK;
}
else BREAK;
}
// Ensure previous transmit of this entry completed
While (macdma_txaddr[NextTxBuffer].EN == 1)
;
Copy data into transmit buffer
Write macdma_txstat[NextTxBuffer] with 0x00000000
Write macdma_txlen[NextTxBuffer] with packet length
Write macdma_txaddr[NextTxBuffer] with address of memory buffer and DN=0,EN=1
Advance NextTxBuffer: if (++NextTxBuffer == 4) NextTxBuffer = 0
This algorithm assumes that the same memory buffer is used for the DMA entry. The transmit algorithm can be changed to
accommodate multiple memory buffers for the DMA entries. It is necessary to write the address of the memory buffer every
time to macdma_txaddr since the DMA engine modifies the value in the register.
9.4.6.6
Ethernet Frame Format
When preparing a frame for transmission, or processing a received frame, it is important to understand the layout of the
Ethernet and IEEE 802.3 frame structure.