58
AMD Alchemy Au1550 Security Network Processor Data Book
DDR/SDR SDRAM Memory Controller
30283D
3.1.1.4
Global Configuration Register B
The global configuration register B contains additional global configuration bits for the SDRAM memory controller.
mem_sdconfigb
Offset = 0x0848
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
EIB
PM
PSEL
CB
DS
CR
BA
TXSR
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:29
—
Reserved.
R/W
0
28
EIB
Enable interrupt on boundary errors for stride mode
0
Disable boundary error interrupts.
1
Enable boundary error interrupts.
R/W
0
27
—
Reserved.
R/W
0
26
PM
Power Mode.
0
Do not negate DCKE to the memory when the chip select is idle.
1
Negate DCKE to the memory when the chip select is idle. This saves
system power by putting the memory either into the active power
down or precharge power down state. The controller still performs
refreshes.
R/W
0
25:24
PSEL
Pin select determines which address pin to use for auto precharge.
00
Address pin 10
01
Address pin 8
1x
Reserved
R/W
0
23:20
—
Reserved.
R/W
0
19
CB
Comparator Bypass.
0
Use the DVREF comparator for input data.
1
Bypass the DVREF comparator for input data.
The CB bit takes effect immediately.
R/W
0
18
—
Reserved.
R/W
0
17
DS
Drive strength for the SDRAM bus signals.
0
Reduced strength
1Full strength
The DRVSEL signal and the DS bit both affect the SDRAM bus signal
strength: For reduced-strength signals, DRVSEL must be tied high and DS
must be cleared; otherwise, the signals are driven at full strength.
R/W
0
16
—
Reserved.
R/W
0
15
CR
Clock ratio. CR is a clock divider between the SBUS clock and the SDRAM
bus clock.
0
Divide the SBUS clock frequency by 2 to derive the SDRAM bus
clock.
1
Run the SDRAM bus clock at the same frequency as the SBUS clock.
mem_sdconfiga[CE] before modifying CR.
R/W
0
14:8
—
Reserved.
R/W
0
7
BA
Block access. When BA is set, the memory controller prevents all transac-
tions for ((TXSR+1) * 16) memory clocks.
This bit must be used when changing anything that affects clocks that go
to memory (i.e., Core PLL multiplier, SBUS divider, CR bit.)
After initiating an access block, software must clear BA.
R/W
0
6:5
—
Reserved.
R
0
4:0
TXSR
Number of NOP commands required on exit from self refresh mode. The
counter is also used when BA is set.
((TXSR+1) * 16) is the actual number used.
R/W
0