368
AMD Alchemy Au1550 Security Network Processor Data Book
EJTAG Implementation
30283D
12.3
Coprocessor 0 Registers
The Coprocessor 0 Registers for EJTAG are shown in
Table 12-1.12.3.1
Debug Register (CP0 Register 23, Select 0)
The Debug register contains the cause of the most recent debug exception and exception in Debug Mode. It also controls
single stepping. Only the DM bit and the EJTAGver field are valid when read from the Debug register in Non-Debug Mode;
the value of all other bits and fields is UNPREDICTABLE.
The following bits and fields are updated only on debug exceptions and/or exceptions in Debug Mode:
DSS, DBp, DINT are updated on both debug exceptions and on exceptions in Debug Modes.
DExcCode is updated on normal exceptions in Debug Mode, and is undefined after a debug exception.
DD is updated on both debug and on normal exceptions in Debug Modes.
Table 12-1. Coprocessor 0 registers for EJTAG
Register
Number
Select
Name
Description
23
0
debug
Debug indications and controls for the processor.
24
0
depc
Program Counter at last debug exception or exception in debug mode.
31
0
desave
Debug exception save register.
debug
CP0 Register 23, Select 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DD DM ND LS
CD
VER
DEXCODE
NS SS
DI
DB DS
Def. x
0000000000000001
xxxxx
0000
x
000
x
Bits
Name
Description
R/W
Default
31
DD
DBD. Indicates whether the last debug exception or exception in debug
mode occurred in a branch or jump delay slot.
0
Not in delay slot
1
In delay slot
R
UNPRED
30
DM
Indicates that the processor is operating in debug mode.
0
Processor is operating in non-debug mode
1
Processor is operating in debug mode
R0
29
ND
NoDCR.
0
drseg is present.
R0
28
LS
LSNM. Controls access of loads/stores between drseg and remaining
memory when drseg is present and while in debug mode.
0
Loads/stores in drseg address range go to drseg
1
Loads/stores in drseg address range go to system memory
R/W
0
27
—
Reserved. This bit is called Doze in the EJTAG 2.5 specification and is not
implemented.
R0
26
—
Reserved. This bit is called Halt in the EJTAG 2.5 specification and is not
implemented.
R0
25
CD
CountDM.
0
Count register stops in debug mode.
R0
24
—
Reserved. This bit is called IBusEP in the EJTAG 2.5 specification and is
not implemented.
R0
23
—
Reserved. This bit is called MCheckP in the EJTAG 2.5 specification and
is not implemented.
R0
22
—
Reserved. This bit is called CacheEP in the EJTAG 2.5 specification and is
not implemented.
R0