AMD Alchemy Au1550 Security Network Processor Data Book
175
Security Engine
30283D
7.3.3.6
Ring Poll Register
The PE ring poll register (sec_glbrpoll) allows programming two polling parameters which are used in the Descriptor Fetch
Engine. The first parameter is the polling frequency at which the security engine reads one descriptor entry of the external
PDR into its internal dual-port command queue.
The second parameter is the re-try interval which specifies how long the security engine should wait in between re-reads on
an invalid descriptor entry (ownership bit not yet assigned to the security engine). The Retry Interval should be set to a
shorter period than the Poll Interval; otherwise, the next poll event preempts a retry. Both of these parameters are typically
used to limit the amount of bus bandwidth that is consumed by the descriptor polling process.
A Read Descriptor interrupt can preempt the poll interval and cause a poll to occur sooner than the timer would dictate. If
this occurs, the timer polling interval is reset to its starting point, thus creating a full delay before the next timed poll.
Also, if descriptors are written directly into the internal dual-port command queue, then this register is ignored. This mode is
configured in sec_glbdmacfg[PE].)
9:0
SIZE
Descriptor Ring Size. Allows the host to specify the Descriptor Ring size
(number of descriptors per ring) for an external descriptor ring. This value
applies to both the PDR and the RDR. Settings of 1 to 1023 represent
valid external ring sizes.
Note: Clearing SIZE specifies that an external PDR is not used. In this
mode, the descriptor fetch engine is disabled, and the host writes descrip-
tors directly into the command queue. The packet engine still writes the
result descriptors to the result descriptor ring, but the RDR size is fixed at
1.
R/W
0
sec_glbrpoll
Offset = 0x0054
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
MBC
RETDIV
POLLDIV
Def. 10000000000001010000000000000000
Bits
Name
Description
R/W
Default
31
MBC
Must be cleared.
R/W
1
30:26
—
Reserved.
R/W
0
25:16
RETDIV
Ring Retry Divisor. Sets a binary value that is used to divide-down the
main security engine clock and arrive at the Retry frequency. Values of 1 –
1,023 provide valid retry intervals. Clearing RETDIV disables retries alto-
gether, and the security engine simply waits until the next poll interval
occurs.
A fixed prescale of 128 is inserted in the main clock prior to the Ring Poll
Divisor.
An example is shown below:
Main security engine clock: 33MHz /128 prescale = 258 kHz
Ring Poll set to 0x0001: Frequency = 258 kHz (3.9 s between retries)
Ring Poll set to 0x03FF: Frequency = 252 Hz (4 ms between retries)
R/W
0
15:12
—
Reserved.
R/W
0
Bits
Name
Description
R/W
Default