AMD Alchemy Au1550 Security Network Processor Data Book
243
AC97 Controller
30283D
8.4.1.3
AC97 Protocol Control Register
The AC97 Protocol Control register is used to control transfers and to clear the Rx and Tx FIFOs. Setting a bit issues a
command to the controller. The bit is automatically cleared once the command is initiated but not necessarily completed.
8.4.1.4
AC97 Status Register
The AC97 Status register contains the status signals for the AC97 protocol. It is read-only. A status condition is true when
the status bit is set. Before the AC97 controller is enabled in psc_ac97cfg[DE], only the device-ready and PSC-ready sta-
tus bits (psc_ac97stat[DR, SR]) are valid; all other status bits read as 0 until ready.
psc_ac97pcr
Offset = 0x0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RC RP RS
TC TP TS
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:7
-
Reserved.
-
0
6
RC
Receive Data Clear. Set this bit to clear the receive FIFO. Do not set this
bit while the receive controller is enabled.
R/W
0
5
RP
Receive Stop. Set this bit to stop the receive controller. Once stopped,
psc_ac97stat[RB] is cleared.
R/W
0
4
RS
Receive Start. Set this bit to start the receive controller. Once started,
psc_ac97stat[RB] is set until the Receive Stop control bit is written a 1 to
stop receiving.
R/W
0
3
-
Reserved.
-
0
2
TC
Transmit Data Clear. Set this bit to clear the transmit FIFO. Do not set this
bit while the transmit controller is enabled.
R/W
0
1
TP
Transmit Stop. Set this bit to stop the transmit controller. Once stopped,
psc_ac97stat[TB] is cleared.
R/W
0
TS
Transmit Start. Set this bit to start the transmit controller. Once started,
psc_ac97stat[TB] is set until the Transmit Stop control bit is written a 1 to
stop sending.
R/W
0
psc_ac97stat
Offset = 0x0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
CB CP CR
RF RE RR TF TE TR
RB TB
DI DR SR
Def. 00000000000000000001001000000000
Bits
Name
Description
R/W
Default
31:27
-
Reserved.
-
0
26
CB
Codec Bit Clock Detected. Indicates the AC97 controller is receiving the
Primary codec bit clock to the PSCn_CLK input port.
R0
25
CP
Command Pending. Indicates a Codec Command is pending on the AC-
link.
R0
24
CR
Codec Ready. Indicates a Codec Ready has been sampled from the previ-
ous AC-frame.
R0
23:14
-
Reserved.
-
0
13
RF
Receive FIFO Full.
R
0
12
RE
Receive FIFO Empty.
R
1
11
RR
Receive Request.
R
0
10
TF
Transmit FIFO Full.
R
0
9
TE
Transmit FIFO Empty.
R
1
8
TR
Transmit Request.
R
0
7:6
-
Reserved.
-
0