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AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
9.4
Ethernet MACs
The Au1550 processor contains two identical and independent Ethernet media access controllers (MACs), each capable of
supporting 10/100 Mbps Ethernet. Each MAC provides the interface between the host application and the PHY layer
through the media independent interface (MII). The PHY layer device is external to the processor.
The MAC supports the protocol requirements to meet the Ethernet/IEEE 802.3 specification. The MAC operates in both half
and full duplex modes. In half duplex mode the MAC is compliant with section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard)
and ANSI/IEEE 802.3.
The MAC provides programmable enhanced features designed to minimize host supervision, bus utilization and pre/post
message processing. These features include the ability to disable retries after a collision, dynamic frame check sequence
(FCS) generation on a frame by frame basis, automatic pad field insertion and deletion to enforce minimum frame size
attributes, automatic retransmission and detection of collision frames. The MAC can sustain transmission or reception of
minimal size back to back packets at full line speed with an inter-packet gap of 9.6 s for 10 Mbps and 0.96 s for
100 Mbps.
A dedicated DMA engine is implemented to support the MAC so that the general purpose DMA is not required.
The primary attributes of the MAC are:
Transmit and receive message data encapsulation with framing and error detection.
Frame boundaries are delimited and frames are synchronized. Error detection is done at the physical medium transmis-
sion level.
Media access management is supported through medium allocation and contention resolution. This is accomplished
through collision avoidance and handling. The MAC handles collision per the ISO 8802.3 specification.
Support for flow control during full duplex mode is accomplished by decoding of control frames and disabling the trans-
mitter in conjunction with generation of control frames.
The MII management interface supports the MII protocol to interface to an MII based PHY.
The MAC features are:
IEEE 802.3, 802.3u, 803.3x specification compliance
10/100 Mbps data transfer rates
IEEE 802.3 compliant MII interface to talk to an external PHY
Full and half duplex
CSMA/CD in half duplex
Flow control support for full duplex
Collision detection and auto retransmit on collisions in half duplex
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Optional automatic Pad stripping on the receive packets.
Loopback support on the MII
Filtering modes supported on the Ethernet side:
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast addresses
— Promiscuous Mode
— Pass all incoming packets with a status report
— Toss bad packets
Separate 32-bit status returned for transmit and receive packets
Jumbo packet (10,240 bytes)
Big/Little Endian data format support