AMD Alchemy Au1550 Security Network Processor Data Book
245
AC97 Controller
30283D
8.4.1.6
AC97 Tx/Rx Data Register
The AC97 Tx/Rx Data Register is the interface to the transmit and receive FIFOs. Each FIFO is 16 entries deep. A write to
this register causes data to be pushed onto the Tx FIFO; if the Tx FIFO is already full, the data is lost and a transmit-over-
flow event is triggered (psc_ac97evnt[TO] = 1). A read from this register causes data to be popped from the Rx FIFO; if the
Rx FIFO is already empty, the data read is undefined and a receive-underflow event is triggered (psc_ac97evnt[RU] = 1).
If transfers are under program control (psc_ac97cfg[DD] = 1), software can monitor the transmit-request (TR) and receive-
request (RR) flags to maintain proper FIFO levels either by polling psc_ac97stat[TR, RR] or by waiting for interrupts in
psc_ac97evnt[TR, RR]. The DDMA controller (psc_ac97cfg[DD] = 0) automatically manages overflow/underflow condi-
tions.
The data size of read/write transfers is always 32-bits to the register; however, AC97 data payloads are limited to a maxi-
mum of 20-bits and a minimum of 8-bits (configured in psc_ac97cfg[LEN]). The upper unused data bits can be left unini-
tialized.
When DMA transfers are enabled, the psc_ac97txrx address locations must be programmed into the Tx descriptor desti-
nation pointer and the Rx descriptor source pointer.
8.4.1.7
AC97 Codec Command Register
The AC97 Codec Command Register controls reads and writes with the external codec(s). A write to this register contains
the codec 2-bit ID, command register index and the R/W bit to indicate the direction of the transfer. If the transfer is to be a
write, the write data must also be included; otherwise, write zeros to the data location (psc_ac97cdc[DATA]).
Upon writing the psc_ac97cdc register, the command-pending status bit is set (psc_ac97stat[CP] = 1), and on the next
AC-link frame the codec ID, index, R/W bit, and data (for a write) are sent out on the AC-link.
When a read or write completes, the command-done flag is set (psc_ac97evnt[CD] = 1), and the command-done interrupt
is generated unless masked. Writes take no more than two AC97-link frames; reads take at least three frames depending
on the codec latency. If the external codec does not respond to a transfer, the command-pending flag remains set and the
command-done event is never triggered.
For codec read commands, once the command-done event occurs, software must read psc_ac97cdc[DATA] before clear-
ing the command-done event flag.
Note:
Reads are supported only from the primary codec. Reads to a secondary codec are ignored.
psc_ac97txrx
Offset = 0x001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DATA
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:20
-
Reserved
--
19:0
DATA
AC97 data values can be between 8 and 20 bits wide. Program the
psc_ac97cfg[LEN] register value accordingly.
R/W
0
psc_ac97cdc
Offset = 0x0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RD
ID
INDX
DATA
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:26
-
Reserved.
-
0
25
RD
Codec Read/Write Command.
0
Write command.
1
Read command.
RD reads as 0 after the command completes (psc_ac97evnt[CD]=1).
R/W
0
24:23
ID
Codec ID. Contains the ID for the codec to be addressed. ID reads as 0s
after the command completes (psc_ac97evnt[CD]=1).
R/W
0