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AMD Alchemy Au1550 Security Network Processor Data Book
PCI 2.2 Bus Controller
30283D
4.1.3
Accesses to Processor Memory from PCI
The Au1550 processor supports one memory window visible from the PCI bus. This memory window can be configured to
a minimum size of 64 KB and a maximum size of 2 GB. The PCI address base of the window is set in the pci_mbar regis-
ter. The location of the window within the Au1550 address space is configured in the pci_wbase register. The size is con-
figured in the pci_wmask register.
Only static memory accesses and SDRAM memory accesses are supported from PCI. Accesses to Au1550 processor
peripherals and non-prefetchable external devices on the static interface are not supported. Also, all reads from Au1550
memory initiated from PCI are prefetched.
The Au1550 processor data cache snoops accesses to memory from PCI if the NC bit is clear in the pci_ config register.
By locking an area of memory into the data cache it is possible to transfer information to and from PCI without causing
external memory cycles.
4.1.4
On-chip PCI Arbiter
The Au1550 processor contains an on-chip PCI arbiter. This arbiter supports 4 external devices and can be disabled if
using an external arbiter. When the on-chip arbiter is enabled, the Au1550 processor has four request inputs and four grant
outputs. When an external arbiter is used, the input PCI_REQ0# is re-defined to be PCI_GNT0#, and the output
PCI_GNT0# is re-defined to be PCI_REQ0#. The other request/grant signals are unused when an external arbiter is used.
A two-level fair algorithm scheme is implemented, which ensures each master access to the bus independent of other
requests. The two levels of arbitration allows bus masters to be assigned high or low priority according to their need to use
the bus. Bus masters with a greater need to use the bus should be assigned to the high priority arbiter versus the low prior-
ity arbiter. As a group, the low priority requests arbitrate into the high priority arbiter. In this way, high-priority bus masters
cannot dominate the bus to the point of excluding low-priority masters which are continually requesting the bus.
Two of the external masters and the Au1550 are configurable for high/low priority. The other two external masters are tied to
either a fixed high or low priority, as shown in
Table 4-3. Priorities must be initialized by software before masters begin to
request use of the PCI bus.
The arbiter implements bus parking so that if no other masters are requesting the use of the bus, the last master to have
ownership of the bus retains that ownership until another request is received. Out of system reset, the Au1550 processor
drives the PCI address bus, C/BE bus and PAR.
If a master receives a grant by requesting the bus and does not initiate a transaction within 16 PCI clocks after receiving the
grant, the master is assumed to be broken and an error is reported in pci_config[BM].
7:0
TO
Target-ready (PCI_TRDY#) timeout. Contains the maximum number of
PCI clocks to wait for PCI_TRDY# assertion before terminating a transfer.
Valid values range from 1 to 255. Clearing TO disables this function, which
means no time limit is placed on waiting for PCI_TRDY#.
R/W
0x80
Table 4-3. PCI Arbiter Priority Configuration
Master
Priority
External Master 3
High Priority
External Master 2
pci_config[2]
External Master 1
pci_config[1]
External Master 0
Low Priority
Au1550
pci_config[0]
Bits
Name
Description
R/W
Default