AMD Alchemy Au1550 Security Network Processor Data Book
27
Au1 Core and System Bus
30283D
Write buffer merging is controlled by the merge-disable bit (Config0[NM]) and the TLB[CCA] setting:
When Config0[NM] is 1, merging is disabled globally, regardless of CCA.
When Config0[NM] is 0 (default value out of reset), merging is enabled globally. However, merging for individual memory
regions can still be controlled by the TLB[CCA] value:
— When CCA is 2, merging is disabled.
— When CCA is not 2, merging is enabled.
Note:
Merging takes place only in the merge latch. As such, writes to an address which are in the FIFO (but not in the
merge latch) do not merge. In the example below, writes to 0x0001000 and 0x0001002 do not merge because the
intervening write to address 0x00001005 is not in the same word address which caused 0x00001000 to leave the
merge latch.
0x00001000 = 0xAB
0x00001005 = 0xCD
0x00001002 = 0xDE
2.4.3
Write Buffer Gathering
Write buffer gathering combines sequentially adjacent word addresses for burst transfers to the main memory. Adjacent
gatherable sequence has its C bit set. The entire sequence is then written to main memory in a single burst the next time
the write buffer is granted the SBUS.
Write buffer gathering is particularly useful for sequential, incremental address store operations, such as string operations.
With write buffer gathering, the stores are combined into bursts up to 32-bytes (eight words) in length which reduces the
number of accesses to the memory and increases effective throughput.
Here is an example of an eight-word burst. The burst could result from code which sequentially writes words (optimized
memcpy(), for example). These eight word writes occur in sequence:
0x00001000
0x00001004
0x00001008
0x0000100C
0x00001010
0x00001014
0x00001018
0x0000101C
The write buffer FIFO entries corresponding to word addresses 0x00001000 through 0x00001018 have the C bits cleared.
When address 0x0000101C arrives, the C bit is set to mark the end of a gatherable sequence. When the write buffer is
granted the SBUS, it bursts all eight entries to main memory.
Here is an example of a two-word burst, typical of application software. These four word writes occur in sequence:
0x00001000
0x00001004
0x0000100C
0x00001008
Based on the above write sequence, the following occurs:
1)
The 0x00001000 entry is placed in the merge latch.
2)
The 0x00001004 entry pushes the 0x00001000 entry with its C bit cleared into the write buffer FIFO.
3)
Because the 0x0000100C entry is not sequential, the 0x00001004 entry is pushed into the FIFO with its C bit set.
Entries 0x00001000 and 0x00001004 are then burst to main memory.
4)
When the 0x00001008 entry arrives, the 0x0000100C entry is pushed into the FIFO with its C bit set. The 0x00001008
entry resides in the merge latch until displaced by a subsequent store.
After this example write sequence, the write buffer appears as in
Figure 2-4 on page 28. The figure shows the two write
requests pending because the write buffer may not be granted immediate access to the SBUS.