156
AMD Alchemy Au1550 Security Network Processor Data Book
Interrupt Controller
30283D
Table 6-4. Interrupt Controller Registers
Offset
(Note 1)
Register
Type
Description
Default
0x0040
ic_cfg0rd
R
Configuration 0 register
Configuration 1 register
Configuration 2 register
The combined field consisting of ic_cfg2[n], ic_cfg1[n],
and ic_cfg0[n] specifies the trigger characteristics for
UNPRED
0x0040
ic_cfg0set
W
0x0044
ic_cfg0clr
W
0x0048
ic_cfg1rd
R
UNPRED
0x0048
ic_cfg1set
W
0x004C
ic_cfg1clr
W
0x0050
ic_cfg2rd
R
UNPRED
0x0050
ic_cfg2set
W
0x0054
ic_cfg2clr
W
0x0054
ic_req0int
R
Shows active interrupts on request 0. Used by software to
determine the interrupt source.
0x0000 0000
0x0058
ic_srcrd
R
Selects the source of the interrupt between a test bit and
the designated source.
0 Use the test bit (ic_testbit[TB]) as interrupt source.
1 Use the peripheral interrupt (for controller 0) or GPIO
signal (for controller 1) as interrupt source.
UNPRED
0x0058
ic_srcset
W
0x005C
ic_srcclr
W
0x005C
ic_req1int
R
Shows active interrupts on request 1. Used by software to
determine the interrupt source.
0x0000 0000
0x0060
ic_assignrd
R
Assigns the interrupt to one of the CPU requests.
0 Assign interrupt to request 1.
1 Assign interrupt to request 0.
UNPRED
0x0060
ic_assignset
W
0x0064
ic_assignclr
W
0x0068
ic_wakerd
R
Controls whether the interrupt can cause a wakeup from
IDLE0 or IDLE1.
0 No wakeup from idle
1 Interrupt causes wakeup from idle.
The associated interrupt must still be enabled to wake from
idle. Setting this bit without setting the associated mask bit
may cause unpredictable IDLE power consumption.
0x0000 0000
0x0068
ic_wakeset
W
0x006C
ic_wakeclr
W
0x0070
ic_maskrd
R
Interrupt enable.
0 Disable the interrupt.
1 Enable the interrupt.
0x0000 0000
0x0070
ic_maskset
W
0x0074
ic_maskclr
W
0x0078
ic_risingrd
R
Designates active rising edge interrupts. If an interrupt is
generated off of a rising edge, the associated rising edge
detection bit must be cleared after detection.
UNPRED
0x0078
ic_risingclr
W
0x007C
ic_fallingrd
R
Designates active falling edge interrupts. If an interrupt is
generated off of a falling edge, the associated falling edge
detection bit must be cleared after detection.
UNPRED
0x007C
ic_fallingclr
W
0x0080
ic_testbit
R/W
This is a single bit register that is mapped to all the source
select inputs for testing purposes.
UNPRED