AMD Alchemy Au1550 Security Network Processor Data Book
257
System Management Bus (SMBus)
30283D
8.5.1.5
SMBus Event Register
The SMBus event register (psc_smbevnt) contains the event flags for the SMBus protocol. When an event flag is set, a
corresponding interrupt is generated unless masked in the SMBus mask register (psc_smbmsk).
Once an event flag has been set, it remains set until cleared. A flag is cleared by writing a 1 to the appropriate bit; writing a
0 has no effect.
8.5.1.6
SMBus Tx/Rx Data Register
The SMBus Tx/Rx Data Register is the interface to the transmit and receive FIFOs. Each FIFO is 16 entries deep. A write to
this register causes data to be pushed onto the Tx FIFO; if the Tx FIFO is already full, the data is lost and a transmit-over-
flow event is triggered (psc_smbevnt[TO] = 1). A read from this register causes data to be popped from the Rx FIFO; if the
Rx FIFO is already empty, the data read is undefined and a receive-underflow event is triggered (psc_smbevnt[RU] = 1).
If transfers are under program control (psc_smbcfg[DD] = 1), software can monitor the transmit-request (TR) and receive-
request (RR) flags to maintain proper FIFO levels either by polling psc_smbstat[TR, RR] or by waiting for interrupts in
psc_smbevnt[TR, RR]. The DDMA controller (psc_smbcfg[DD] = 0) automatically manages overflow/underflow condi-
tions.
The data size of read/write transfers is always 32-bits to the register; however, the SMBus data payload is fixed at 8 bits,
and the upper 24 bits must be cleared except for the data flow control bits (STP and RSR). For programmed I/O, these bits
can be written to control a Master transfer. The data flow control bits are taken care of automatically when using DMA.
psc_smbevnt
Offset = 0x0018
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DN AN AL
RR RO RU TR TO TU
SD MD
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31
-
Reserved.
-
0
30
DN
Data Not-acknowledged. Applies to master mode only. Indicates Tx data
sent from the SMBus in master mode was not acknowledged by the slave.
R/W
0
29
AN
Address Not-acknowledged. Applies to master mode only. Indicates the
slave address sent from the SMBus in master mode was not acknowl-
edged by any slave.
R/W
0
28
AL
Arbitration Lost. Applies to master mode only. Indicates the SMBus in mas-
ter mode has lost arbitration and could not successfully retry a transfer.
R/W
0
27:14
-
Reserved.
-
0
13
RR
Receive Request. Applies to programmed I/O only (psc_smbcfg[DD]=1).
Indicates the Rx FIFO has a number of data elements equal to the FIFO
threshold programmed in psc_smbcfg[RT] available for reading.
R/W
0
12
RO
Receive Overflow. Indicates the Rx FIFO has experienced an overflow.
R/W
0
11
RU
Receive Underflow. Indicates the Rx FIFO has experienced an underflow.
R/W
0
10
TR
Transmit Request. Applies to programmed I/O only (psc_smbcfg[DD]=1).
Indicates the Tx FIFO is requesting a number of data elements equal to
the FIFO threshold programmed in psc_smbcfg[TT].
R/W
0
9
TO
Transmit Overflow. Indicates the Tx FIFO has experienced an overflow.
R/W
0
8
TU
Transmit Underflow. Indicates the Tx FIFO has experienced an underflow.
R/W
0
7:6
-
Reserved.
-
0
5
SD
Slave Done. This flag indicates that a slave transfer has completed
R/W
0
4
MD
Master Done. This flag indicates that a master transfer has completed.
R/W
0
3:0
-
Reserved.
-
0