AMD Alchemy Au1550 Security Network Processor Data Book
177
Security Engine
30283D
7.3.3.9
Packet Engine I/O Threshold Register
The packet engine I/O threshold register (sec_glbthresh) specifies the input buffer and the output buffer thresholds to con-
trol when the packet engine begins to transfer packet data. These parameters control the DMA burst size for the packet
data flow in and out of the packet engine. The burst size setting in the sec_dmaburst register also limits transfer sizes; see
7.3.3.10
Input Data FIFO Register
The packet engine input data FIFO register (sec_indata) is the FIFO input location for the 64-byte input buffer. The host
can monitor the available bytes in the input buffer through the packet engine DMA status register; see
Section 7.3.3.2 "DMANote:
This register is used exclusively by the packet engine DMA engine. The Host should not write to this register
except for debug purposes.
7.3.3.11
Output Data FIFO Register
The packet engine output data FIFO register (sec_outdata) is the FIFO output location for the 64-byte output buffer. The
host can monitor the available bytes in the output buffer through the packet engine DMA status register; see
Section 7.3.3.2Note:
This register is used exclusively by the packet engine DMA engine. The Host should not read this register except
for debug purposes.
sec_glbthresh
Offset = 0x0060
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
OT
IT
Def. 00000000000010000000000000001000
Bits
Name
Description
R/W
Default
31:20
—
Reserved.
R/W
0
19:16
OT
Output Threshold. These bits indicate how many 32-bit words (0-15) must
be available in the PE output buffer prior to initiating a DMA output transfer.
R/W
0x8
15:4
—
Reserved.
R/W
0
3:0
IT
Input Threshold. These bits indicate how many 32-bit entries (0-15) must
be available in the PE input buffer prior to initiating a DMA input transfer.
R/W
0x8
sec_indata
Offset = 0x06A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
INDATA
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Bits
Name
Description
R/W
Default
31:0
INDATA
Input data.
W
UNDEF
sec_outdata
Offset = 0x06A4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
OUTDATA
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Bits
Name
Description
R/W
Default
31:0
OUTDATA
Output data.
R
UNDEF