264
AMD Alchemy Au1550 Security Network Processor Data Book
System Management Bus (SMBus)
30283D
Programmed I/O Back-to-Back Transfers
To perform a back-to-back Master transfer in programmed I/O mode, the last byte of the first (or subsequent) transfer is writ-
ten with a 1 in the restart data flow control bit (psc_smbtxrx[RSR]). This causes the SMBus master controller to generate
a RESTART condition on the bus after this byte has been processed. For a read transfer, the SMBus generates a NOT-
ACKNOWLEDGE
condition for the last Rx data byte.
Back-to-back master transfers can be chained together, as needed, using this flow control protocol. Write the stop data flow
control bit (psc_smbtxrx[STP]) for the last Tx byte of the last transfer in the chain. This causes the SMBus controller to
generate a STOP condition on the bus following the last byte for a write transfer or a NOT-ACKNOWLEDGE for a read transfer.
Initiating a Master Transfer
Once the data has been set up for a master transfer, set the master-start bit (psc_smbpcr[MS]) to start the SMBus master
controller. The SMBus controller begins the master transfer as soon as the Tx address control byte is present in the Tx
FIFO. At this point the SMBus controller arbitrates for the bus (or waits if the bus is busy) and then proceeds with the master
transfer.
Upon successful completion of a master transfer, a master-done interrupt is generated unless masked. When using DMA
the master-done interrupt is generated after a STOP condition has been generated on the bus and all Rx data (if receiving)
has been written to memory. When using the SMBus in programmed I/O mode, a master-done interrupt is generated imme-
diately following the STOP condition on the bus (regardless of Rx FIFO status).
If a master transfer fails (arbitration lost, address NOT-ACKNOWLEDGE, or data NOT-ACKNOWLEDGE), the appropriate interrupt
is generated unless masked, and the transfer terminates without completing.
8.5.2.5
SMBus Slave Operation
The SMBus controller is ready for Slave mode accesses once it has been enabled. At this point the SMBus controller
responds to its slave address (or a GENERAL CALL if enabled). Data flow must be prepared in order for the SMBus controller
to respond to a slave transfer.
DMA Transfers
For Slave write transfers, prepare Tx descriptors as needed. For Slave read transfers, prepare Rx descriptors.
The Tx buffers are transmitted if the SMBus controller is addressed as a Slave for a Master read transfer (SMBus Slave ->
external Master). Each Tx data byte is sent out during the Master read. If the Master read completes before a Tx buffer fin-
ishes, the buffer remains open for the next Master read transfer.
The Rx buffers are used if the SMBus controller is addressed as a Slave for a Master write transfer (external Master ->
SMBus Slave). Each Rx data byte is written to the Rx buffer. If the Master write completes before the end of a Rx buffer, the
Rx buffer is closed and the next Rx buffer is used for the next Master write transfer.
Programmed I/O Transfers
For programmed I/O, software writes the Tx data bytes directly to the Tx FIFO or reads Rx data bytes directly from the Rx
FIFO via the psc_smbtxrx data register. Software can send one byte at a time by writing to psc_smbtxrx and then waiting
for the Tx FIFO underflow event (psc_smbevnt[TU] = 1). The SMBus controller holds the bus (SCL low) until a new Tx data
byte is forthcoming. Also the SMBus controller holds the bus (SCL low) if an Rx FIFO overflow occurs
(psc_smbevnt[RO] = 1). Once there is room in the Rx FIFO, the SMBus controller releases SCL and continues.
Transfer Completion
The SMBus controller generates a slave-done event (psc_smbevnt[SD] = 1) at the completion of each slave transfer
(detects a STOP or RESTART on the bus). When using DMA the interrupt is generated once all Rx data has been written to
memory (Master write to SMBus), or immediately following the STOP/RESTART detection (Master read from SMBus). If using
the SMBus in programmed I/O mode, the Slave Done interrupt is generated immediately following the STOP/RESTART detec-
tion regardless of Rx FIFO status.