314
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
9.4.4.2
MAC DMA Transmit Registers
There are three transmit registers, including the status register, the address/enable register, and the length register. In the
naming of the receive registers dummy variables m and n have been inserted into the name to designate MAC number (m)
and buffer number (n).
Transmit Packet Status Register
This register contains the transmit packet status bits sent by the MAC after transmitting a frame. This register is valid after a
transmit transaction has been enabled by the host and the done bit has been set by the MAC in the Address/Enable Regis-
ter to signify that the transmit transaction is complete.
If either PR (bit 31) or FA (bit 0) is set, then the frame was not sent successfully and the application resends the frame.
macdmam_txnstat
Offset = 0x0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PR
CC
LO DF UR EC LC ED LS NC JT FA
Def. XXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXX
Bits
Name
Description
R/W
Default
31
PR
Packet Retry.
0
Transmission of current packet is complete.
1
The Application has to restart the transmission of the frame (packet)
when this bit is set to ‘1’. The successful/unsuccessful completion of
the frame’s transmission is indicated by the Frame Aborted bit (bit 0).
R
UNPRED
30:14
—
Reserved.
R
UNPRED
13:10
CC
Collision Count. This 4-bit count indicates the number of collisions that
occurred before the frame was transmitted. This bit is not valid when the
Excessive Collisions bit is set.
This bit is valid only when the MAC is operating in half-duplex mode.
R
UNPRED
9
LO
Late Collision Observed.
0
No late collision observed during transmission.
1
Indicates that the MAC observed a late collision (collision after 64
bytes into transmission of frame), but retransmitted the frame in the
next retransmission attempt. This bit is set when the Late Collision bit
is set.
This bit is valid only when the MAC is operating in half-duplex mode.
R
UNPRED
8
DF
Deferred.
0
Transmitter did not defer when transmitting.
1
The transmitter had to defer while ready to transmit a frame.
This bit is valid only when operating in half-duplex mode.
R
UNPRED
7
UR
Under Run.
0
No data under run
1
The transmitter aborted the message because of data under run dur-
ing the frame’s transmission.
R
UNPRED
6
EC
Excessive Collisions.
0
Transmission did not abort due to excessive collisions.
1
Transmission aborted after 16 successive collisions. If the Disable
Retry bit is set, this bit is set after the first collision and the transmis-
sion of the frame is aborted.
This bit is valid only when operating in half-duplex mode.
R
UNPRED
5
LC
Late Collision.
0
No late collision.
1
Transmission was aborted due to collision occurring after the collision
window of 64 bytes. This bit is not valid if under run error is set.
This bit is valid only when operating in half-duplex mode.
R
UNPRED