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AMD Alchemy Au1550 Security Network Processor Data Book
Descriptor-Based DMA (DDMA) Controller
30283D
Figure 5-1. DDMA Controller Block Diagram
Each channel contains a write-only doorbell register (ddman_dbell) which is used to activate the channel. When software
writes to ddman_dbell, the DDMA controller fetches the descriptor, loads it into the channel’s local descriptor buffer, and
clears the doorbell. The controller then examines the descriptor to determine the transfer type and attributes. The controller
asserts a channel request to the channel arbiter to obtain the System Bus (SBUS) for the transfer; see
Section 5.1.1 "Chan-The process of asserting channel requests and arbitrating for the SBUS continues until all data is transferred in accordance
with the descriptor. After the transfer is complete, the DDMA controller updates the status of the current descriptor in mem-
ory and marks it completed if no error occurred. The status pointer register contains the address of the status word to be
written to the descriptor upon completion. The controller also generates an interrupt, if enabled.
The pointer to the next descriptor is read from the current descriptor and loaded into the local descriptor pointer register.
This pointer is then used to load the next descriptor from memory. The DDMA controller continues to fetch descriptors and
transfer data until it encounters a nonvalid descriptor (dscr_cmd0[V] = 0) or software disables the channel
(ddman_cfg[EN] = 0).
Transfers can occur using multiple descriptors.
5.1.1
Channel Priority and Arbitration
Each channel is assigned to either a high priority pool or a low priority pool. The channel arbiter checks the high priority
pool up to eight times for every one time for the low priority pool. The DDMA controller places a channel request into either
the high or low priority pool based on the arbitration bit in the descriptor command0 field (dscr_cmd0[ARB]); refer to
Figure For each pool, the channel arbiter supports two arbitration policies, round-robin and weighted priority:
For weighted priority, the arbiter sorts the request by channel number, with channel 0 having the highest priority and
channel 15 having the lowest.
For round-robin priority, the arbiter selects the channels with equal priority, stepping through all requesting channels
before starting over.
As part of the configuration of the DDMA controller, software selects the arbitration policies using ddma_config[AH] for the
high priority pool and ddma_config[AL] for the low priority pool.
DDMA
Controller
Channel n Local
Descriptor Buffer
Descriptor 0
Descriptor 1
Source
Memory Buffer
or FIFO
Destination
Memory Buffer
or FIFO
Channel n
Descriptors
Descriptor x
Channel 0 Local
Descriptor Buffer
Channel 1 Local
Descriptor Buffer
Channel 15 Local
Descriptor Buffer
Channel Arbiter
dscr_cmd0[ARB]
High Pool
Arbitration
Policy
Low Pool
Arbitration
Policy
Priority
Logic
Request
for
SBUS