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AMD Alchemy Au1550 Security Network Processor Data Book
Interrupt Controller
30283D
6.2.2
Test-bit Register
6.3
Hardware Considerations
To use a GPIO as an interrupt source the pin functionality in the sys_pinfunc register must be for a GPIO; see
Section 6.4
Programming Considerations
The Au1550 processor has been designed to simplify interrupt management by removing the need for a semaphore to con-
trol access to the registers. There is no need to perform a read-modify-write sequence because separate registers are pro-
vided for setting and clearing bits. In this way software can freely manipulate the interrupts associated with that application.
If using edge-triggered interrupts, it is important to clear the associated edge detection bit to allow subsequent interrupts to
be detected.
Interrupts are programmed as follows: (The set, clr, and rd portion of the register name has been omitted.)
1)
Identify the interrupt number, n, with the associated peripheral or GPIO.
2)
Use ic_src[n] to assign the interrupt to the associated peripheral/GPIO (or the test bit can be used if testing the inter-
rupt).
3)
Set the ic_cfg2[n], ic_cfg1[n] and ic_cfg0[n] bits to the correct configuration for the corresponding interrupt (edge,
level, polarity).
4)
Assign the interrupt to a CPU request using ic_assign[n].
5)
Use ic_wake[n] to assign the interrupt to wake the processor from IDLE if necessary, or clear this register bit to keep
the interrupt from waking the processor from IDLE.
6)
If the interrupt is an edge-triggered interrupt, clear the edge detect register (ic_risingclr or ic_fallingclr) before
enabling.
7)
Finally, enable the interrupt through ic_mask[n].
When servicing an interrupt, follow these steps:
1)
Read ic_req0int and ic_req1int to determine the interrupt number n.
2)
Use ic_fallingrd and ic_risingrd to determine if the interrupt is edge-triggered. If so, use ic_fallingclr[n] or
ic_risingclr[n] to clear the edge detection circuitry.
3)
If the interrupt is to be disabled write ic_maskclr[n].
4)
Service the interrupt.
ic_testbit
Offset = 0x0080
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
TB
Def. XXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXX
Bits
Name
Description
R/W
Default
31:1
—
Reserved.
R/W
UNPRED
0
TB
Test bit value used as an alternate interrupt source.
R/W
UNPRED