AMD Alchemy Au1550 Security Network Processor Data Book
111
PCI 2.2 Bus Controller
30283D
The Au1550 processor has the option to boot from the PCI bus, if BOOT[2:0] is equal to 4. Therefore, the default value of
CM_BASE and CM_MASK point to the MIPS boot vector of 0x1FC00000.
4.1.1.2
PCI Configuration/Error Register
The pci_config register configures the general operation of the PCI interface. It allows configuration of the Au1550 on-chip
bits can be used in conjunction with the PCI Status register defined in the PCI 2.2 specification.
Bits [13:8] are the PCI interrupt enables. These enables can be used to assist debug by only interrupting on specific condi-
tions. All 6 interrupts are OR-ed together to create one interrupt signal back to the interrupt controller. If an interrupt is dis-
abled, the specific condition does not assert the PCI interrupt.
pci_cmem
Offset = 0x0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
HC
E
CM_BASE
CM_MASK
Def. Rs
00
Rs
0001111111000011111111111111
Bits
Name
Description
R/W
Default
31
HC
PCI Host Configuration Indicator. Reflects the value of the PCI configura-
tion signal PCI_CFG.
0
Satellite configuration. (PCI_CFG is low.)
1
Host configuration. (PCI_CFG is high.)
R
Depends on
PCI_CFG signal
30:29
—
Reserved
R
0
28
E
Enable.
0
Disable PCI cacheable memory.
1
Enable PCI cacheable memory.
R/W
Depends on
BOOT[2:0] (see
27:14
CM_BASE
Specifies bits [31:18] of the starting/base address for the PCI cacheable
memory region.
R/W
0x7F0
13:0
CM_MASK
Specifies which bits of physical_addr[31:18] are used to decode the PCI
cacheable memory region.
R/W
0x3FFF
pci_config
Offset = 0x0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
ERRADDRH
ERD ET
EF
EP
EM
BM
PD BME
NC
IA
IP
IS
IMM ITM ITT IPB
SIC
ST
SM AEN R2H R1H CH
Def. 00000000000100000000000000000000
Bits
Name
Description
R/W
Default
31:28
ERRADDRH
These bits are the upper bits [35:32] of the error address. The lower 32 bits
R/W
0
27
ERD
PCI error occurred on a read/write#. If an error is detected for a PCI
access, ERD reflects the direction of the transaction.
0
Error occurred on a write.
1
Error occurred on a read.
R/W
0
26
ET
PCI error occurred while the Au1550 was a target.
R/W
0
25
EF
PCI fatal error detected. These errors include Master and Target Aborts as
well as certain errors not specified in the PCI Specification, but which may
be important to the user.
R/W
0
24
EP
PCI parity error detected. Parity errors are detected either by the Au1550
bus interface on data it receives, or by the target device on the PCI bus
and passed to the Au1550 via PCI_PERR#.
R/W
0
23
EM
Multiple PCI errors detected. If an error was detected while EF or EP is
asserted, EM is set.
R/W
0
22
BM
PCI Arbiter detected bad master. Does not assert PCI_FRAME# (or
negate PCI_REQ[n]#) within 16 clocks of being granted the PCI bus.
R/W
0