308
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
9.4.3
MAC Enable Registers
Each Ethernet MAC has an identical enable register. Both enable registers are located off of the macen_base shown in
9.4.3.1
MAC0 and MAC1 Enable Registers
The enable register for each MAC contains a bit that enables the entire block. The block is disabled if not in use to minimize
power consumption. In addition, each enable register contains a toss bit (TS) which prevents frames that do not pass the
address filter from being put into memory.
The process for bringing the MAC out of reset is as follows:
1)
Enable clocks (CE=1).
2)
Bring E[2:0] high together with the other bits configured as desired (keeping clocks enabled).
MAC clocks must be running before the internal MAC registers are accessed.
macen_mac0
Offset = 0x0000
macen_mac1
Offset = 0x0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
IPG
JP E2 E1 C TS E0 CE
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:9
—
Reserved.
W
0
8:7
IPG
Inter-Packet Gap. Determines the inter-packet gap measured in bit times.
For example, the minimum IPG for 100 Mbps full-duplex Ethernet is 960 bit
times (0.960 s).
00
1080 (default)
01
1040
10
1000
11
960 (for IEEE 802.3 minimum IPG compliance)
W0
6
JP
Jumbo Packet Enable.
0
Normal (Max packet length = 0x0800 bytes)
1
Enable Jumbo Packet (Max packet length = 0x2800 bytes)
W0
5:4
E[2:1]
Enable Field Bits 2 and 1. Together with E0, this field resets and enables
the MAC.
000 Reset
111 Enable
All other combinations are invalid.
W00
3
C
Coherent.
0
Memory accesses are marked coherent on SBUS.
1
Memory accesses are marked non coherent on SBUS.
W0
2TS
Disable Toss.
0
Only frames passing the address filter are passed to memory.
Frames which fail length error, CRC error, or other non-address filter
failures are still passed to memory.
Frames are not passed to memory if the filter fail bit is set, or the
frame is a broadcast frame and broadcast frames have been dis-
abled.
In promiscuous mode all frames are passed to memory unless the
disable broadcast bit is set which prevents broadcast frames from
being passed to memory.
Frames that are not passed to memory are transparent to software—
no status or indication informs software.
1
All frames are passed to memory regardless of address filter result.
W
UNPRED