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AMD Alchemy Au1550 Security Network Processor Data Book
Features
30283D
1.2
Features
High Speed MIPS CPU Core
■ 333, 400, or 500 MHz
■ MIPS32 instruction set 32-bit architecture
■ 1.2V nominal core voltage
■ 3.3V or 2.5V SDRAM I/O voltage, 3.3V I/O voltage
■ Pipeline:
— Scalar 5-stage pipeline
— Load/store adder in I-stage (instr decode)
— Scalar branch techniques optimized: Pipelined
register file access in fetch stage
— Zero penalty branch
■ Multiply-Accumulate (MAC) and Divide Unit:
— Max issue rate of one 32x16 MAC per clock
— Max issue rate of one 32x32 MAC per every other
clock
— Operates in parallel to CPU pipeline
— Executes all integer multiply and divide instructions
— 32x16-bit MAC hardware
■ Caches:
— 16 KB non-blocking data cache
— 16 KB instruction cache
— Instruction and data caches are 4-way
set associative
— Write-back with read-allocate
— Cache Management Features:
– Programmable allocation policy
– Line locking
— Prefetch instructions (instruction and data)
— High speed access to on-chip buses
Highly-Integrated System Peripherals
■ GPIO (43 total, 10 dedicated for system use)
■ Two 10/100 Ethernet MAC controllers
■ USB 1.1 device and host controllers with On-The-Go
(OTG) support
■ Four programmable serial controllers (PSC) supporting
AC97, I2S, SPI, SMBus
■ Three UARTs
■ PCI 2.2 compatible interface
■ PCMCIA interface
Security Engine
■ Accelerates both IPsec and SSL type VPN standards in
hardware
■ Direct support for DES, 3DES, AES, ARC4, SHA1, MD5
■ Full IPsec packet protocol processing implemented in
hardware
■ True entropy-based random number
generator (RNG) in hardware
Descriptor-based DMA (DDMA)
■ Linked list of DMA transfer descriptors
■ Scatter/gather (SGL) and stride transfers
■ 16 channels
■ Memory to memory, memory to peripheral, peripheral to
memory, peripheral to peripheral
Memory Buses
■ High-bandwidth DDR or SDR SDRAM memory
controller (supports up to DDR400)
■ SRAM/Flash EPROM controller with NOR/NAND Flash
support
MMU
■ TLB Features:
— 32 dual-entry fully-associative
— Variable page sizes: 4 KB to 16 MB
—4-entry ITB
■ Separate TLB miss interrupt exception vector
Low System Power
■ Core / Power:
— 333 MHz / 400 mW
— 400 MHz / 500 mW
— 500 MHz / 600 mW
■ Power-Saving Modes:
—Idle
—Sleep
— Hibernate
Package
■ 483 BGA (Ball Grid Array), 21x21 mm
Operating System Support
■ Microsoft Windows CE
■ Linux
■ VxWorks
Development Tool Support
■ Complete MIPS32 Compatible Tool Set
■ Numerous 3rd-Party Compilers, Assemblers and
Debuggers