AMD Alchemy Au1550 Security Network Processor Data Book
395
Signal Descriptions
30283D
Ethernet Controller 1
N1TXCLK
I
Continuous clock input for synchronization of transmit
data. 25 MHz when operating at 100 Mbps and 2.5
MHz when operating at 10 Mbps.
IN
N1TXEN
O
Indicates that the data on N1TXD[3:0] is valid. Muxed
with GPIO[24]. GPIO[24] is the default signal coming
out of hardware reset, runtime reset, and Sleep.
NA
N1TXD[3:0]
O
4-bit wide data bus synchronous to N1TXCLK. For
each N1TXCLK period in which N1TXEN is asserted,
TXD[3:0] presents valid data to the PHY. While
N1TXEN is negated the data presented on TXD[3:0] is
not valid.
Muxed with GPIO[28:25]. GPIO[28:25] are the default
signals coming out of hardware reset, runtime reset,
and Sleep.
NA
N1RXCLK
I
Continuous clock that provides the timing reference for
the data transfer from the PHY to the MAC. N1RXCLK
is sourced by the PHY. N1RXCLK must have a fre-
quency equal to 25% of the data rate of the received
signal data stream (typically 25 MHz at 100 Mbps and
2.5 MHz at 10 Mbps).
IN
N1RXDV
I
Indicates that a receive frame is in process and that
the data on N1RXD[3:0] is valid.
IN
N1RXD[3:0]
I
RXD[3:0] is a 4-bit wide data bus driven by the PHY to
the MAC synchronous with N1RXCLK. For each
N1RXCLK period in which N1RXDV is asserted,
RXD[3:0] transfers four bits of recovered data from the
PHY to the MAC. While N1RXDV is negated, RXD[3:0]
has no effect on the MAC.
IN
N1CRS
I
The PHY asserts N1CRS when either transmit or
receive medium is non idle. The PHY negates N1CRS
when both the transmit and receive medium are idle.
N1CRS is an asynchronous input.
IN
N1COL
I
The PHY asserts N1COL upon detection of a collision
on the medium and continues to assert N1COL while
the collision condition persists. N1COL is an asyn-
chronous input. The N1COL signal is ignored by the
MAC when operating in full duplex mode.
IN
N1MDC
O
N1MDC is sourced by the MAC to the PHY as the tim-
ing reference for transfer of information on the
N1MDIO signal. N1MDC is an aperiodic signal that
has no maximum high or low times. The N1MDC fre-
quency is fixed at SBUS clock divided by 160.
0UN
LV
N1MDIO
IO
N1MDIO is the bidirectional data signal between the
MAC and the PHY that is clocked by N1MDC.
Requires an external 1.5 kohm pull-up resistor.
0UN
LV
Table 13-3. External Signals (Continued)
Signal
Type
Description
Reset
During
Sleep
HW
Run
Time