AMD Alchemy Au1550 Security Network Processor Data Book
77
Static Bus Controller
30283D
3.2.1.1
Static Bus Configuration Registers
The static bus configuration registers (mem_stcfgn) configure the basic properties of each chip select. Support is included
for static RAM, NOR and NAND Flash, ROM, PCMCIA, and other types of I/O devices.
When programming a chip select as an I/O, or PCMCIA device the address comparison mask expects an address with
sysbus_addr[35:32] set as shown in
Table 3-9 on page 79 for the different device types. The TLB must be set up accord-
ingly to map addresses to the memory region captured by the associated chip select.
If mapped to the first 512 Mbytes, addresses for RAM and Flash device types do not need translation in the TLB because
they map directly to KSEG0/1 (sysbus_addr[35:32] = 0x0).
mem_stcfg0
Offset = 0x1000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
NW AS S DE
BEB
TA
DIV
AV BE TS EW H BS PM RO
DTY
Def. 000000000
Rs
0
Rs
001001100000
Rs Rs
000
Rs
mem_stcfg1
mem_stcfg2
mem_stcfg3
Offset = 0x1010
Offset = 0x1020
Offset = 0x1030
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
NW AS S DE
BEB
BE TS EW H BS PM RO
DTY
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Bits
Name
Description
R/W
Default
31:23
—
Reserved.
—
22
NW
NAND Width. Selects the device width for NAND Flash. Applies
to NAND Flash devices only (DTY = 5).
0
16-bit mode.
1
8-bit mode.
R/W
0 if BOOT[2:0] = 0, 1, 4, or 6
1 if BOOT[2:0] = 7
21
AS
Setup Address before output enable on reads. The setup dura-
tion is programmed in mem_sttimen[T1, T0] and is shown as
0
Do not setup address.
1
Setup address.
R/W
0
20
S
Synchronous mode for this chip select. This bit does not apply
to NAND operation.
0
Asynchronous mode. All static bus signals are synchro-
nized to the internal SBUS clock. Values in the
mem_sttimen register are programmed in system-bus-
clock resolution.
1
Synchronous mode. All static bus signals are synchro-
nized to RCLK. Values in the mem_sttimen register are
programmed in RCLK clock resolution.
Note: Synchronous mode must not be selected when config-
ured for PCMCIA.
Note: If S is set in NAND mode, the NAND signal timings are
still based off the SBUS, and all timing parameters are still pro-
grammed in system-bus-clock resolution.
R/W
0 if BOOT[2:0] = 1, 4, 6, or 7
1 if BOOT[2:0] = 0
19
DE
Deassert chip select, output enable, write enable, and byte
enables between each beat during bursts. The deassert time is
programmable via mem_sttimen[Tcsoff].
Note: A one-word (32-bit) transfer to a 16-bit bus is treated as a
R/W
0