AMD Alchemy Au1550 Security Network Processor Data Book
123
PCI 2.2 Bus Controller
30283D
Table 4-7 shows the supported modes for the SM, ST and SIC bits based on the endianness of the processor.
4.2.12
System Considerations
The Au1550 PCI controller cannot be used with external PCI-to-PCI bridges that have PCI bus-mastering devices on the
secondary bus which target the Au1550 memory.
If the parity enable bit is cleared, the Au1550 asserts PCI_DEVSEL# on target writes in one PCI_CLK. If the parity error
enable bit is set, the Au1550 processor drives PCI_DEVSEL# in two cycles of PCI_CLK on target writes.
The Au1550 processor does not generate or respond to Dual Address Cycles. External PCI masters must not send Dual
Address Cycles to the Au1550 processor.
The Au1550 processor does not respond to I/O Cycles. External PCI masters must not send I/O cycles to the Au1550 pro-
cessor.
The Au1550 processor does not respond to Special Cycles. External PCI masters must not send Special cycles to the
Au1550 processor.
The Au1550 processor can generate both Type 0 and Type 1 configuration cycles in host mode. Only Type 0 Configuration
cycles are decoded by the Au1550 processor in satellite mode.
The PCI_SERR# signal is only an output. The Au1550 processor attempts to complete transactions which receive a
PCI_SERR#.
The Memory Write and Invalidate command is not supported by the Au1550. Setting the Memory Write and Invalidate
capable bit in the PCI configuration header has no effect.
The Au1550 processor supports PCI cacheline sizes of eight or four 32-bit words.
4.2.13
Hardware Considerations
If the PCI clock is generated internally, PCI_CLKO must be tied to PCI_CLK through a 12 ohm resistor for 66 MHz oper-
ation or through a 22 ohm resistor for 33 MHz operation.
For Host mode, PCI_CFG must be pulled high. For Satellite mode, PCI_CFG must be pulled low.
PCI specification calls for pull-ups on all control signals of the PCI bus (PCI_FRAME#, PCI_TRDY#, PCI_IRDY#,
PCI_DEVSEL#, PCI_STOP#, PCI_SERR#, PCI_PERR#, PCI_LOCK#, PCI_INT[A:D]#.) Refer to the PCI specification
for resistor values.
Each unconnected PCI_REQ[3:0]# requires a weak pull-up.
The PCI controller is designed for both 66 MHz and 33 MHz operation. Each PCI bus speed is specified separately, with
minimum and maximum limits based upon a nominal test circuit. The limits are based on a line impedance of 40 < Zo <
60 ohms. The designer must sum the capacitance of the traces and all devices for each pin to create the total capaci-
tance limit.
Table 4-7. Supported Endian/Swapping Modes
Mode
Big Endian
Little Endian
SM
yes
ST
yes
SIC = 00
no
yes
SIC = 01
yes (only affects I/O transactions)
no
SIC = 10
yes
no
SIC = 11
yes
no
Table 4-8. PCI Bus Limits
PCI Clock Speed
66 MHz
33 MHz
Maximum Load Capacitance
40 pF
100 pF
Maximum Trace Length
9 inches
12 inches