AMD Alchemy Au1550 Security Network Processor Data Book
375
EJTAG Implementation
30283D
6
DU
Data Store to Uncached Area. This bit enables the comparison on proces-
sor address and data bus for data store to the uncached area.
0
Processor address and data is not compared for storing data into the
un-cached area.
1
Processor address and data is compared for storing data into the un-
cached area.
R/W
UNPRED
5:4
DIU
Data or Instruction Fetch or Load from Uncached Area. These bits enable
the comparison on processor address and data bus for data or instruction
load and fetch from the un-cached area.
00
Processor address and data is not compared for loading data or
fetching instructions from the un-cached area.
11
Processor address and data is compared for loading data or fetching
instruction from the un-cached area.
Bits 5 and 4 were named ILUC and DFUC in the EJTAG 2.0.0 specification
and were implemented separately for instruction and data fetches.
R
UNPRED
3
OE
Overlay Enable. When this bit is 1 and the processor physical address,
masked by the HAM, UOAM and the LAM fields (all 36 bits of the address
mask), matches the PHAB and PAB registers, then the memory request is
redirected to the EJTAG Probe.
When OE is set, the processor bus break cannot be used for the normal
break function. Therefore, BE (break-enable) must be cleared; otherwise,
the behavior is undefined.
The overlay feature is valid only for memory regions. It is not valid for I/O
or debug space, and the behavior is unpredictable if addresses within this
space are used.
R/W
0
2
—
Reserved. This bit is called TE in the EJTAG 2.0.0 specification and is not
implemented.
R0
1
—
Reserved. This bit is called CBE in the EJTAG 2.0.0 specification and is
not implemented.
R0
0
BE
Break Enable. This bit enables the processor bus break function.
0
Processor bus break function is disabled.
1
Processor bus break function is enabled.
If BE is set and the processor physical address, masked by the HAM and
the LAM fields (UOAM is only for overlay so bits 31:24 are not masked
here), matches the PHAB and PAB registers, and the processor data bus
matches the PDB register (masked by PDM), then a debug exception to
the processor is generated.
The BS bit in the Processor Bus Break Status register is set and the DINT
bit in the Debug Register is set. If the debug exception handler is already
running (DM=‘1’), then the debug exception is not taken until DM = 0.
This functionality is mutually exclusive to OE so only one of OE or BE must
be set at any time.
R/W
0
Bits
Name
Description
R/W
Default