AMD Alchemy Au1550 Security Network Processor Data Book
325
Secondary General Purpose I/O
30283D
9.5.1.1
Direction Register
The gpio2_dir register controls the direction of each GPIO2 signal. This register controls only the output enable for the out-
put buffer. Clearing a bit in this register disables the output for the corresponding pin making it possible to read an externally
driven input.
An open drain can be emulated on a GPIO2 pin as follows:
Add a pull-up resistor to the GPIO2 pin.
Clear the corresponding data bit in the gpio2_output register.
Use gpio2_dir to configure the GPIO2 signal as an input to allow the signal to be pulled high and as an output to drive
the signal low.
9.5.1.2
Data Output Register
The gpio2_output register controls the output data for the GPIO2 signals. Data bits 15:0 are output to the corresponding
GPIO2 signal when the corresponding enable bit is set during a write to this register. For example, to output a ‘1’ on
GPIO[200] and a ‘0’ on GPIO[201] without changing the output of any other GPIOs, write the value 0x00030001 to
gpio2_output.
gpio2_dir
Offset = 0x0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
DIR
Def. 00000000000000000000000000000001
Bits
Name
Description
R/W
Default
31:16
—
Reserved.
R
0
15:0
DIR
Direction Control. Each bit controls the I/O direction of one GPIO signal in
the secondary block. Bits 15:0 correspond to GPIO[215:200].
0
Pin is an input (output disabled).
1
Pin is an output.
The GPIO[200] default direction is out because GPIO[200] is designed to
act as a PCI reset output signal (PCI_RSTO#) if needed.
R/W
0x0001
gpio2_output
Offset = 0x0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
ENA
DATA
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:16
ENA[15:0]
Data Output Write Enable. ENA[15:0] corresponds to DATA[15:0]. ENA is
write-only and should be ignored on reads.
0
Disable modifications to corresponding bit in DATA[15:0].
1
Enable modifications to corresponding bit in DATA[15:0].
W0
15:0
DATA[15:0]
Output Data. DATA[15:0] corresponds to GPIO[215:200]. The DATA bit val-
ues are reflected in the corresponding GPIO output signal value.
When modifying a bit in DATA[15:0], the corresponding bit in ENA[15:0]
must be set at the same time to allow the write. This mechanism allows
individual data bits to be modified without affecting DATA[15:0] as a whole.
R/W
0