Table 67: Derating Values for tDS/tDH – AC135/DC100-Based
Shaded cells indicate slew rate combinations not supported
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew
Rate V/ns
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0
68
50
68
50
68
50
1.5
45
34
45
34
45
34
53
42
1.0
0
8
16
0.9
2
–4
2
–4
10
4
18
12
0.8
0.7
0.6
0.5
0.4
Table 68: Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid Transition
Slew Rate (V/ns)
tVAC at 175mV (ps)
tVAC at 150mV (ps)
tVAC at 135mV (ps)
Min
>2.0
75
175
187
2.0
57
170
165
1.5
50
167
121
1.0
38
163
50
0.9
34
162
20
0.8
29
161
n/a
0.7
22
159
n/a
0.6
13
155
n/a
0.5
0
150
n/a
<0.5
0
150
n/a
2Gb: x4, x8, x16 DDR3 SDRAM
Data Setup, Hold, and Derating
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
107
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