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| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 194/210页 |
| 文件大小： | 12448K |
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Notes: 1. Parameters are applicable with 0°C
≤ TC ≤ +95°C and VDD/VDDQ = +1.5V ±0.075V.
2. All voltages are referenced to VSS.
3. Output timings are only valid for RON34 output buffer selection.
4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock edges.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environ-
ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/
DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew
rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/
ns for differential inputs in the range between VIL(AC) and VIH(AC).
6. All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine
In the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is VDDQ/
2 for single-ended signals and the crossing point for differential signals (see Figure 30
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK(AVG) as a long-term jitter component; however, the spread spec-
trum may not use a clock rate below tCK (AVG) MIN.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con-
secutive clocks and is the smallest clock half period allowed, with the exception of a
deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed
values specified and must be of a random Gaussian distribution in nature.
13. The period jitter (tJITper) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
14. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one ris-
ing edge to the following falling edge.
15. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
ing edge to the following rising edge.
16. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error (tERRnper), where n is the number of clocks between 2 and
50, is the amount of clock time allowed to accumulate consecutively away from the aver-
age clock over n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
84
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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