Figure 68: Consecutive READ Bursts (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Don’t Care
Transitioning Data
T12
T13
T14
tRPST
NOP
READ
NOP
CK
CK#
Command1
DQ3
DQS, DQS#
Bank,
Col n
Bank,
Col b
Address2
RL = 5
tRPRE
tCCD
RL = 5
DO
n + 3
DO
n + 2
DO
n + 1
DO
n
DO
n + 7
DO
n + 6
DO
n + 5
DO
n + 4
DO
b + 3
DO
b + 2
DO
b + 1
DO
b
DO
b + 7
DO
b + 6
DO
b + 5
DO
b + 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
Figure 69: Consecutive READ Bursts (BC4)
NOP
CK
CK#
Command1
DQ3
DQS, DQS#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Address2
T10
T11
Don’t Care
Transitioning Data
T12
T13
T14
READ
NOP
Bank,
Col n
Bank,
Col b
tRPST
tRPRE
tRPST
tRPRE
RL = 5
DO
n + 3
DO
n + 2
DO
n + 1
DO
n
DO
b + 3
DO
b + 2
DO
b + 1
DO
b
RL = 5
tCCD
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
157
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2006
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