Figure 85: Consecutive WRITE (BL8) to WRITE (BL8)
WL = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCCD
tWPRE
T10
T11
Don’t Care
Transitioning Data
T12
T13
T14
Valid
NOP
WRITE
NOP
CK
CK#
Command1
DQ3
DQS, DQS#
Address2
tWPST
tWR
tWTR
tBL = 4 clocks
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
DI
b + 3
DI
b + 2
DI
b + 1
DI
b
DI
b + 7
DI
b + 6
DI
b + 5
DI
b + 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
T0 and T4.
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF
WL = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCCD
tWPRE
T10
T11
Don’t Care
Transitioning Data
T12
T13
T14
Valid
NOP
WRITE
NOP
CK
CK#
Command1
DQ3
DQS, DQS#
Address2
tWPST
tWR
tWTR
tWPST
tWPRE
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
b + 3
DI
b + 2
DI
b + 1
DI
b
tBL = 4 clocks
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. BC4, WL = 5 (AL = 0, CWL = 5).
3. DI n (or b) = data-in for column n (or column b).
4. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
169
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2006
Micron
Technology,
Inc.
All
rights
reserved.