![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_40.png)
Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8
IDD Test
IDD6: Self Refresh Current
Normal Temperature Range
TC = 0°C to +85°C
IDD6ET: Self Refresh Current
Extended Temperature Range
TC = 0°C to +95°C
CKE
LOW
Midlevel
External clock
Off, CK and CK# = LOW
Midlevel
tCK
n/a
tRC
n/a
tRAS
n/a
tRCD
n/a
tRRD
n/a
tRC
n/a
CL
n/a
AL
n/a
CS#
Midlevel
Command inputs
Midlevel
Row/column addresses
Midlevel
Bank addresses
Midlevel
Data I/O
Midlevel
Output buffer DQ, DQS
Enabled
Midlevel
Enabled, midlevel
Midlevel
Burst length
n/a
Active banks
n/a
None
Idle banks
n/a
All
SRT
disabled (normal)
enabled (extended)
n/a
ASR
disabled
n/a
Notes: 1. "Enabled, midlevel" means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid once power is stable
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + tRFC.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Definitions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
40
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