- 您现在的位置：买卖IC网 > PDF目录299522 > MT41J128M16HA-107:D 128M X 16 DDR DRAM, PBGA96 PDF资料下载
参数资料
| 型号： | MT41J128M16HA-107:D |
| 元件分类： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封装： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件页数： | 86/210页 |
| 文件大小： | 12448K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页当前第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页
PRECHARGE Operation
Input A10 determines whether one bank or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
SELF REFRESH Operation
The SELF REFRESH operation is initiated like a REFRESH command except CKE is
LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automati-
cally enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid lev-
els upon entry/exit and during self refresh mode operation. VREFDQ may float or not
drive VDDQ/2 while in the self refresh mode under certain conditions:
VSS < VREFDQ < VDD is maintained
VREFDQ is valid and stable prior to CKE going back HIGH
The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid
All other self refresh mode exit timing requirements are met
The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) (page 189) for timing re-
quirements). If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH
command internally within the tCKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
tCK specifications) when self refresh mode is entered. If the clock remains stable and
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the
clock is altered during self refresh mode (turned-off or frequency change), then tCKSRE
and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE must be satis-
fied prior to altering the clock's frequency. Prior to exiting self refresh mode, tCKSRX
must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS
is required for the completion of any internal refresh that is already in progress and
must be satisfied before a valid command not requiring a locked DLL can be issued to
the device. tXS is also the earliest time self refresh reentry may occur. Before a com-
mand requiring a locked DLL can be applied, a ZQCL command must be issued,
tZQoper timing must be met, and tXSDLL must be satisfied. ODT must be off during
tXSDLL.
2Gb: x4, x8, x16 DDR3 SDRAM
PRECHARGE Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
176
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MT45W2MW16BBB-856WT | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| MT46H32M32LGCM-5IT:A | 32M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46HC32M16LFCX-75:B | 32M X 16 DDR DRAM, 7.5 ns, PBGA90 |
| MT46HC32M16LGCM-54IT:B | 32M X 16 DDR DRAM, 5.4 ns, PBGA90 |
| MT47H32M16BT-37VL:A | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。