Figure 93: WRITE (BC4 OTF) to PRECHARGE
WL = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
Don’t Care
Transitioning Data
Bank,
Col n
NOP
WRITE
PRE
NOP
CK
CK#
Command1
DQ4
DQS, DQS#
Address3
tWPST
tWPRE
Indicates A Break In
Time Scale
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
tWR2
Valid
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR speci-
fies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data
mask setup and hold timings are measured relative to the DQS, DQS# crossing, not the
clock crossing.
The WRITE preamble and postamble are also shown here. One clock prior to data input
to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is
driven LOW (DQS# is driven HIGH) during the WRITE preamble, tWPRE. Likewise, DQS
must be kept LOW by the controller after the last data is written to the DRAM during the
WRITE postamble, tWPST.
Data setup and hold times are shown. All setup and hold times are measured from the
crossing points of DQS and DQS#. These setup and hold values pertain to data input
and data mask input.
Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL.
2Gb: x4, x8, x16 DDR3 SDRAM
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
174
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2006 Micron Technology, Inc. All rights reserved.