![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_197.png)
Table 88: Synchronous ODT Parameters
Symbol
Description
Begins at
Defined to
Definition for All
DDR3
Speed Bins
Units
ODTL on
ODT synchronous turn-on delay
ODT registered HIGH
RTT,on ±tAON
CWL + AL - 2
tCK
ODTL off
ODT synchronous turn-off delay
ODT registered HIGH
RTT,off ±tAOF
CWL +AL - 2
tCK
ODTH4
ODT minimum HIGH time after ODT
assertion or WRITE (BC4)
ODT registered HIGH or
write registration with ODT HIGH
ODT registered LOW
4tCK
tCK
ODTH8
ODT minimum HIGH time after
WRITE (BL8)
Write registration with ODT
HIGH
ODT registered LOW
6tCK
tCK
tAON
ODT turn-on relative to ODTL on
completion
Completion of ODTL on
RTT,on
ps
tAOF
ODT turn-off relative to ODTL off
completion
Completion of ODTL off
RTT,off
0.5tCK ± 0.2tCK
tCK
Figure 114: Synchronous ODT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CWL - 2
AL = 3
tAON (MAX)
tAOF (MAX)
T10
T11
T12
T13
T14
T15
CK
CK#
RTT
ODT
Don’t Care
Transitioning
RTT,nom
CKE
tAOF (MIN)
ODTL off = CWL + AL - 2
ODTL on = CWL + AL - 2
ODTH4 (MIN)
tAON (MIN)
Note: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT,nom is enabled.
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
197
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