![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_160.png)
Figure 74: READ to PRECHARGE (BC4)
CK
CK#
Don’t Care
Transitioning Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
Command
NOP
ACT
NOP
READ
NOP
PRE
Address
Bank a,
Col n
Bank a,
(or all)
Bank a,
Row b
tRP
tRTP
DQS, DQS#
DQ
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
tRAS
Figure 75: READ to PRECHARGE (AL = 5, CL = 6)
CK
CK#
Command
NOP
Address
DQ
DQS, DQS#
Don’t Care
Transitioning Data
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
NOP
READ
Bank a,
Col n
NOP
PRE
Bank a,
(or all)
ACT
Bank a,
Row b
NOP
tRAS
CL = 6
AL = 5
tRTP
tRP
DO
n + 3
DO
n + 2
DO
n
DO
n + 1
Figure 76: READ with Auto Precharge (AL = 4, CL = 6)
CK
CK#
Command
NOP
Address
DQ
DQS, DQS#
Don’t Care
Transitioning Data
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Ta0
tRTP (MIN)
NOP
READ
NOP
AL = 4
NOP
CL = 6
NOP
tRAS (MIN)
ACT
Indicates A Break in
Time Scale
tRP
Bank a,
Col n
Bank a,
Row b
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
2Gb:
x4,
x8,
x16
DDR3
SDRAM
PDF:
09005aef826aaadc
2Gb_DDR3_SDRAM.pdf
–
Rev.
K
04/10
EN
160
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Technology,
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2006
Micron
Technology,
Inc.
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reserved.