![](http://datasheet.mmic.net.cn/200000/MT41J128M16HA-107-D_datasheet_15084792/MT41J128M16HA-107-D_144.png)
Mode Register 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
grammed via the LOAD MODE command and retains the stored information until it is
programmed again or until the device loses power. Reprogramming the MR3 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR3 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time tMRD and tMOD before initiating a sub-
sequent operation.
Figure 58: Mode Register 3 (MR3) Definition
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode register 3 (MR3)
Address bus
9
7
6
5
4
3
8
2
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
14
15
A13
A14
01
01 01 01 01 01
01
MPR
1
BA2
16
17
01
01 01 01
M2
0
1
MPR Enable
Normal DRAM operations2
Dataflow from MPR
MPR_RF
M15
0
1
0
1
M16
0
1
Mode Register
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
MPR READ Function
Predefined pattern3
Reserved
M0
0
1
0
1
M1
0
1
Notes: 1. MR3[17 and 14:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-
fined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-
ing the MRS command, all banks must be in the idle state (all banks are precharged,
and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands
are redirected to the multipurpose register. The resulting operation when either a READ
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see
allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] =
0). Power-down mode, self refresh, and any other nonREAD/RDAP commands are not
allowed during MPR enable mode. The RESET function is supported during MPR ena-
ble mode.
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
144
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