Table 12: IDD Measurement Conditions for Power-Down Currents
Name
IDD2P0 Precharge
Power-Down
IDD2P1 Precharge
Power-Down
IDD2Q Precharge
Quiet
Standby Current
IDD3P Active
Power-Down
Current
Timing pattern
n/a
CKE
LOW
HIGH
LOW
External clock
Toggling
tCK
tCK (MIN) IDD
tCK(MIN) IDD
tCK (MIN) IDD
tRC
n/a
tRAS
n/a
tRCD
n/a
tRRD
n/a
tRC
n/a
CL
n/a
AL
n/a
CS#
HIGH
Command inputs
LOW
Row/column addr
LOW
Bank addresses
LOW
DM
LOW
Data I/O
Midlevel
Output buffer DQ, DQS
Enabled
Enabled, off
Burst length
8
Active banks
None
All
Idle banks
All
None
Special notes
n/a
Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast
exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2.
“Enabled, off“ means the MR bits are enabled, but the signal is LOW.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Definitions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
35
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